Data programming circuit for programmable read only memory device

• US 4,791,612 A
• Filed: 12/17/1986
• Issued: 12/13/1988
• Est. Priority Date: 12/18/1985
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshida, Masanobu
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/942,895
• Time in Patent Office: 727 Days
• Field of Search: 365/189, 365/230, 365/195
• US Class Current: 365/189.09
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A programming circuit for a programmable read only memory device receiving a data signal to be programmed including a power supply terminal for receiving a first voltage in a read mode and a second voltage as a programming voltage which is a higher voltage than the first voltage in a program mode; an inverter circuit for converting an amplitude of the data signal in the program mode, the inverter including a load element and a first transistor having a drain connected to the load element and a gate receiving the data signal; and a switching circuit connected between the power source terminal and the load element for supplying the second voltage in the program mode and inhibiting a supply of the first voltage in the read mode.

Claims

1. A programming circuit for a programmable read only memory device receiving a data signal to be programmed, said circuit comprising:

means for receiving the data signal;

a power supply terminal for receiving a first voltage in a read mode and a second voltage as programming voltage which is a higher voltage than said first voltage in a program mode;

an inverter circuit for inverting said data signal in said program mode, said inverter including a load element and a first transistor having a drain connected to said load element and a gate connected to said means for receiving said data signal; and

a switching circuit connected between said power supply terminal and said load element for supplying said second voltage to the load element in said program mode and inhibiting a supply of said frist voltage to the load element in said read mode.

2. A programming circuit according to claim 1, wherein said switching circuit comprises a P channel transistor having a source connected to said power supply terminal, a drain connected to said load element, and a gate connected to voltage supplying means for supplying a voltage to the gate such that said P channel transistor is turned off when the first voltage is supplied to said power supply terminal.

3. A programming circuit according to claim 1, further comprising a second transistor having gate connected to said drain of said first transistor, a drain connected to said switching circuit, and a source for outputting a programming current in response to said data signal.

4. A programming circuit according to claim 3, further comprising a constant current source which is connected in series with said second transistor.

5. A programming circuit according to claim 4;

wherein said constant current source comprises a depletion type transistor having a gate and a source connected in common.