High speed memory system for use with a control bus bearing contiguous segmentially intermixed data read and data write request signals

• US 4,792,926 A
• Filed: 12/09/1985
• Issued: 12/20/1988
• Est. Priority Date: 12/09/1985
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Roberts, Barry R.
• Primary Examiner(s): Fears, Terrell W.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/806,427
• Time in Patent Office: 1,107 Days
• Field of Search: 365/73, 365/189, 365/230, 365/194, 365/239, 365/233
• US Class Current: 365/189.02
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A high speed memory system for 100% bandwidth use with a control bus bearing contiguous sequentially intermixed data read and data write signals including a first buffer for reading data from a storage means into the data bus and a second buffer for writing data from the data bus into the storage means and a memory control sensitive to the order of received write requests and read requests signals to avoid any simultaneous utilization of the data bus and storage means in accordance with a prearranged schedule of preferential utilization of the data bus and storage means. The subject invention and related method further contemplates the employment of a plurality of input/output ports which are responsive to data read and/or data write request signals on the control bus for reading data from and/or writing data into the data bus in synchronism with the utilization of the first and second buffers.

Claims

1. A high speed memory system for use with a control bus bearing sequentially intermixed data read and data write request signals and a data bus, said system comprising:

(a) storage means for holding data;

(b) first means, coupled to said storage means and said data bus, for reading data from said storage means onto said data bus in three sequential cycles comprising a request cycle during which a data read request signal appears on said control bus, a data read access cycle during which data is transferred by said first means from said storage means to said first means, and a data read transfer cycle during which said first means transfers said data from said first means to said data bus;

(c) second means, coupled to said storage means and said data bus, for writing data from said data bus into said storage means in three sequential cycles comprising a request cycle during which a data write request signal appears on said control bus, a data read access cycle during which data is transferred by said second means from said data bus to said second means, and a data write transfer cycle during which said second means transfers said data from said second means to said storage means;

(d) memory control means, coupled to said control bus and to said first and second means, for controlling operation of said first means in response to a data read request signal on said control bus and for controlling operation of said second means in response to a data write request on said control bus to permit contiguous sequential receipt and subsequent execution of said sequentially intermixed data read and write request signals on said control bus by arbitrating operation of said data read access cycles, data write access cycles, data read transfer cycles and data write transfer cycles to prevent potential clashes, in the form of attempts by said first and second means to simultaneously utilize said data bus or to simultaneously utilize said memory means, by selective delay of said data read access, data write access, data read transfer, or data write transfer cycles.

2. A system of claim 1 wherein said first means comprises a data read buffer and said second means comprises a data write buffer.

3. A system of claim 2 wherein said memory control means includes means for resolving said potential clashes in favor of said data write buffer.

4. A system of claim 1 including a plurality of port means, responsive to said data read and/or data write request signals on said control bus, for reading data from and/or writing data into said data bus in synchronism with said operation of said first and second means.

5. A high speed memory system comprising:

(a) a data bus;

(b) a control bus;

(c) means for placing data read and data write request signals on said control bus;

(d) storage means for holding data;

(e) a memory control including;

(i) a memory data read buffer means, including a memory data read buffer memory coupled between said data bus and said storage means, for transferring data from said storage means to said memory data read buffer memory in response to a MEMORY READ ACCESS signal and for transferring data from said memory data read buffer memory to said data bus in response to a MEMORY READ DATA signal;

(ii) a memory data write buffer means, including a memory data write buffer memory coupled between said data bus and said storage means, for transferring data from said data bus to said memory write data memory in response to a MEMORY WRITE DATA signal and for transferring data from said memory data write buffer memory to said storage means in response to MEMORY WRITE ACCESS signal;

(iii) memory logic means, coupled between said control bus and said memory data read and memory data write buffer means, for generating said MEMORY READ ACCESS and MEMORY READ DATA signals in response to data read request signals received from said control bus, and for generating said MEMORY WRITE DATA and MEMORY WRITE ACCESS signals in response to data write request signals received from said control bus; and

for preventing simultaneous generation of MEMORY READ DATA and MEMORY WRITE DATA signals and simultaneous generation of MEMORY READ ACCESS and MEMORY WRITE ACCESS signals to thereby permit contiguous sequential receipt and subsequent execution of sequentially intermixed data read and data write request signals on said control bus.

6. A system of claim 5 wherein said memory logic means includes means for delaying any MEMORY READ DATA signal until no additional MEMORY WRITE DATA signal is required and for delaying any MEMORY READ ACCESS signal until no additional MEMORY WRITE ACCESS signal is required.

7. A system of claim 5 further including a plurality of data ports each of which includes a port data read buffer means for transferring data from said data bus in response to a PORT READ SIGNAL and/or a port data write buffer means for transferring data to said data bus in response to a PORT WRITE DATA signal, each of said data ports further including port logic means for generating said PORT READ DATA signal in response to a data read request signal on said control bus for that port, and for generating said PORT WRITE DATA signal in response to a data write signal on said control bus for that port;

and, in response to data read and data write request signals on said control bus, for synchronizing generation of said PORT READ DATA and PORT WRITE DATA signals with generation by said memory logic of corresponding MEMORY READ DATA and MEMORY WRITE DATA signals, respectively.

8. A method for high speed operation of a memory system, comprising the steps of:

(a) generating data read requests on a control bus to transfer data from a storage for holding data over a data bus to a selected port in sequential READ DATA FROM STORAGE and WRITE DATA INTO DATA BUS cycles;

(b) generating data write requests on said control bus to transfer data from a selected port over sadd data bus to said storage in sequential READ DATA FROM DATA BUS and WRITE DATA INTO STORAGE cycles, said data write requests and data read requests being contiguously and sequentially intermixable on said control bus;

(c) preventing simultaneous READ DATA FROM STORAGE and WRITE DATA INTO STORAGE and simultaneous WRITE DATA ONTO DATA BUS and READ DATA FROM DATA BUS CYCLES by detecting from said data read requests and data write requests on said control bus when simultaneous READ DATA FROM STORAGE and WRITE DATA INTO STORAGE and simultaneous WRITE DATA ONTO DATA BUS and READ DATA FROM DATA BUS cycles are scheduled to occur by delaying selected ones of the READ DATA FROM STORAGE, WRITE DATA INTO STORAGE, WRITE DATA ONTO DATA BUS, and READ DATA FROM DATA BUS cycles to prevent simultaneous READ DATA FROM STORAGE and WRITE DATA INTO STORAGE cycles and to prevent simultaneous WRITE DATA ONTO DATA BUS and READ DATA FROM DATA BUS cycles.

9. A method of claim 8 including the further step of transferring, at said ports in response to data read requests and data write requests on said control bus, data between those ports and said data bus as a function of said delaying of said selected ones of said cycles.