Single wafer moated process

• US 4,794,092 A
• Filed: 11/18/1987
• Issued: 12/27/1988
• Est. Priority Date: 11/18/1987
• Status: Expired due to Term

• Current Assignee: Grumman Aerospace Corporation (Northrop Grumman Corporation)
• Original Assignee: Grumman Aerospace Corporation (Northrop Grumman Corporation)
• Inventors: Solomon, Allen L.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): QUACH, TUAN N
• Application Number:
  US07/122,178
• Time in Patent Office: 405 Days
• Field of Search: 437/208, 437/23, 437/48, 437/49, 437/50, 437/51, 437/67, 437/3, 437/53, 437/225, 148/DIG. 135, 148/DIG. 164, 156/630, 156/632, 156/633, 156/636, 156/646, 250/211 R, 250/332, 357/30, 357/32, 357/41, 357/45
• US Class Current: 438/109
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/035 Diffusion through a layer
• CPC Class Codes: Y10S 148/164 Three dimensional processing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

The present invention is directed to the construction of an integrated circuit chip, and to the method of making such a chip from a plate or wafer. In accordance with the present invention a chip is formed to have conductive edge portions disposed on an insulator surface, which portions optionally may further be expanded into a pad. The insulating material electrically isolates the conductive edge portions from the semiconductive body of the chip. The invention may be implemented in redundant fashion to effect a multiplicity of electrical connections to a set of bulk semiconductor integrated circuits formed on the wafer.

Each exposed conductive portion on a chip edge and its optional surrounding conductive pad may be reliably surrounded by insulator so that electrical shorts to non-insulating regions are not experienced. By this edge surface structure integrated circuit elements may be stacked in an array, and electrically connected at the edge surfaces thereof, without hazard that any electrical regions of the integrated circuit elements may be contacted, save intentionally through a conductive lead or film connected to the pads.

Claims

1. A method of forming an integrated circuit chip from a wafer wherein the doped portions of the wafer are electrically isolated from edge portions thereof, comprising:

forming a plurality of grooves in a wafer;

selectively doping a first surface of the wafer;

depositing insulating material within the grooves;

forming conductive lead upon the first surface of said wafer, said conductive lead extending to and across at least a portion of said grooves;

thinning the wafer such that said grooves extend the entire thickness of the wafer;

trimming longitudinal edge portions of the wafer so that the length of the wafer is bounded by portions of said grooves and the insulating material therein; and

depositing conductive material along the longitudinal edge portions of the wafer, said conductive material being in electrical communication with at least one of the conductive leads formed on the surface of the wafer, said conductive material being isolated by said insulating material from the wafer, except through said at least one of the conductive leads.

2. The method as recited in claim 1 wherein the step of depositing first insulating material within the grooves is performed before the step of thinning the wafer.

3. The method as recited in claim 1 wherein the step of depositing a first insulating material within the grooves is performed after the step of thinning the wafer.

4. The method as recited in claim 1 further comprising the step of applying a first insulating layer upon the first surface of the wafer prior to forming the conductive lead, and selectively etching the insulating layer to facilitate electrical communication between the conductive lead and the doped wafer surface.

5. The method as recited in claim 4 wherein the first insulating layer is formed to extend across substantially the length of the wafer.

6. The method as recited in claim 5 further comprising the step of applying a second layer of insulating material upon the wafer first surface.

7. The method as recited in claim 6 further comprising forming a plurality of said integrated circuit chips and disposing said chips in vertical array.

8. A method of making a multilayer monolithic electrical circuit structure upon a planar wafer which structure presents at, and in the plane of, an edge surface of said wafer (i) a butt end of a conductive lead at least partially bordered by (ii) insulating material, said method comprising:

providing a groove in the planar wafer;

providing a body of insulating material within the groove;

routing a conductive lead transversely onto the groove and upon the insulating material therein;

shaping the edge surface of the wafer at the location of said groove so that both (i) a butt end of the conductive lead and the (ii) insulating material of the moat are exposed on the edge surface of the wafer;

wherein the butt end of the conductive lead is at the edge surface bordered by the insulating material of the moat.

9. A wafer fabrication method of making an edge surface of a multilayer monolithic electrical circuit chip so that a butt end of a conductive lead is presented at the edge surface, the method comprising:

forming a groove in a planar surface of a wafer;

placing a first insulating material within the groove;

routing a plurality of conductive leads transversely onto the groove and upon the first insulating material thereof;

placing a second insulating material about any exposed surface of the plurality of conductive leads;

thinning the wafer until the first insulating material of the moat is exposed;

shaping a wafer edge surface along the groove and perpendicular to the plane of the wafer, therein exposing at the edge only the first insulating material and the second insulating material with butt ends of the plurality of conductive leads sandwiched therebetween.

10. A method of forming an integrated circuit chip suitable for abutting electrical connection to external electronics comprising:

forming a plurality of grooves in the surface of a semiconductive wafer having a length and a thickness, said grooves extending a portion of the thickness of the wafer;

depositing a layer of insulating material within the grooves;

forming active circuitry on a first surface of the wafer, said active circuitry including conductive leads, at least one of the conductive leads extending across at least a portion of the grooves;

thining the wafer so that the grooves extend the entire thickness of the wafer;

trimming the length of the wafer so that the length of the wafer is defined by the grooves; and

depositing a section of conductive material along a first edge surface of the wafer, said section of conductive material being effective to facilitate electrical communication between the conductive leads and external electronics.

11. The method as recited in claim 10 wherein the step of forming active circuitry includes doping a portion of the semiconductive wafer and applying said conductive leads to the first surface of the wafer, said at least one of said conductive leads being in electrical communication with said doped portions.

12. The method as recited in claim 10 wherein said step of trimming the length of the wafer includes the step of trimming a portion of the grooves and exposing an edge portion of said at least one of the conductive leads to facilitate electrical communication with the active circuitry.

13. The method as recited in claim 10 wherein the step of depositing a body of insulating material comprises filling the grooves to substantially the surface of the wafer with an insulating material.

14. The method as recited in claim 10 wherein the step of depositing a body of insulating material within the grooves comprises depositing a layer of silicon dioxide within the grooves.

15. The method as recited in claim 10 further including the step of depositing a body of insulating material upon the wafer first surface to encase the active circuitry.

16. The method as recited in claim 10 further including the step of depositing a layer of insulating material upon the wafer first surface and selectively removing portions of the insulating layer above at least one section of the active circuitry.

17. A method of forming an integrated circuit for abutting electrical connection to external electronics comprising:

forming a plurality of grooves in the surface of a semiconductive wafer, said wafer having a length, a thickness and an upper surface, said grooves extending a portion of the thickness of the wafer;

filling the grooves with a first body of insulating material;

forming doped semiconductor regions on the upper surface of the semiconductor material;

depositing a second body of insulating material along the upper surface of the wafer, said layer of insulating material covering said doped regions and extending across the insulating material within the grooves;

selectively applying conductive leads on the upper surface of the wafer, said leads being in electrical communication with said doped regions and extending across at least a portion of said body of insulating material;

selectively removing portions of the second body of insulating material adjacent the active doped regions;

thinning the wafer so that the grooves extend the entire thickness of the wafer;

trimming the length of the wafer so that lengthwise edges of the wafer are defined by the grooves and that at least one of said conductive leads are exposed at lengthwise edges of the wafer, and

depositing conductive material along the lengthwise edges of the wafers, said conductive material being in electrical communication with said at least one of said conductive lead and effective to facilitate electrical communication between the doped regions and external electronics.

18. A method of forming a single wafer integrated circuit for abutting electrical connection to external electronics comprising:

forming a plurality of grooves in the surface of a semiconductive wafer, said wafer having a length, a thickness and an upper surface, said grooves extending a portion of the thickness of the wafer;

filling the grooves with a first body of insulating material;

forming doped semiconductor regions on the upper surface of the semiconductor material;

depositing a second body of insulating material along the upper surface of the wafer, said layer of insulating material covering said doped regions and extending across the insulating material within the grooves;

selectively removing portions of the second body of insulating material adjacent the active doped regions;

selectively applying conductive leads on the upper surface of the wafer, said leads being in electrical communication with said doped regions, at least one of said leads extending across at least a portion of said body of insulating material;

thinning the wafer so that the grooves extend the entire thickness of the wafer;

trimming the length of the wafer so that lengthwise edges of the wafer are defined by the grooves and that at least one of said conductive leads is exposed at a lengthwise edge of the wafer; and

depositing conductive material along the lengthwise edges of the wafers, said conductive material being in electrical communication with said at least one of said conductive leads and effective to facilitate electrical communication between the doped regions and external electronics.