Fault indicator having improved trip inhibit circuit

• US 4,794,332 A
• Filed: 03/28/1986
• Issued: 12/27/1988
• Est. Priority Date: 03/28/1986
• Status: Expired due to Term

• Current Assignee: Edmund O. Schweitzer III, Jean E. Schweitzer, Marilyn L. Schweitzer
• Original Assignee: Edmund O. Schweitzer Jr
• Inventors: Schweitzer, Edmund O. Jr.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Solis, Jose M.
• Application Number:
  US06/845,591
• Time in Patent Office: 1,005 Days
• Field of Search: 324/133, 324/509, 324/512, 324/522, 340/664, 340/654, 340/662, 361/94, 361/110, 361/59, 361/87
• US Class Current: 324/133
• CPC Class Codes: G01R 19/16509 using electromagnetic relays, e.g. reed relay magnetically driven reeds G01R9/06

Abstract

A fault indicator for indicating the occurrence of a fault current in a monitored conductor includes an electrically actuated indicator flag. Trip circuitry within the fault indicator conditions the indicator flag from a normal reset-indicating state to a fault-indicating state upon the occurrence of a fault current in the conductor. Improved high impedance trip inhibiting circuitry inhibits the trip function following a loss of voltage in the conductor whereby the fault indicator is rendered insensitive to inrush current during a period immediately following restoration of power to the system.

Claims

1. A fault indicator for indicating the occurrence of a fault current in an electrical conductor of an alternating current distribution power system, wherein the conductor is subject to inrush current levels in excess of fault current levels upon power up of the conductor, comprising:

status indicating means having reset-indicating and fault-indicating states;

a trip capacitor;

trip circuit means operable from said trip capacitor for conditioning said status indicating means to said fault-indicating state in response to the occurrence of a fault current in the conductor;

a trip inhibit capacitor;

charge circuit means powered by alternating current in the monitored conductor for developing a charge current for charging said trip capacitor to a predetermined charge level;

delay circuit means operable upon interruption of said charge current for establishing current flow between said trip capacitor and said trip inhibit capacitor, the terminal voltage across said trip inhibit capacitor progressively increasing with said current flow; and

trip inhibit circuit means responsive to the voltage across said trip capacitor increasing beyond a predetermined threshold level for discharging said trip capacitor to render said trip circuit means inoperative and the fault indicator non-responsive to inrush current in the conductor.

2. A fault indicator as defined in claim 1 wherein the capacitance of said trip inhibit capacitor is substantially less than the capacitance of said trip capacitor.

3. A fault indicator as defined in claim 1 wherein said charge circuit means comprise a circuit capacitively coupled to the monitored conductor.

4. A fault indicator as defined in claim 3 wherein said trip and trip inhibit capacitors are connected in series across the output of said rectifier circuit, and wherein are included voltage limiting means connected across said trip inhibit capacitor for limiting the voltage developed across said capacitor by said charge current.

5. A fault indicator as defined in claim 4 wherein said delay means comprise a resistor connected between the unconnected terminals of said capacitors.

6. A fault indicator as defined in claim 1 wherein said trigger circuit means comprise a control effect generating device and a transistor, said transistor having a first main electrode connected to the connected terminal of said capacitors, and a second main electrode connected through said generating device to the non-connected terminal of said trip capacitor, and a gate electrode connected to the non-connected terminal of said trip inhibit capacitor, and further having between said gate electrode and said first main electrode a threshold voltage level above which conduction is initiated between said main electrodes.

7. A fault indicator as defined in claim 6 wherein said transistor is a field effect transistor.

8. A fault indicator as defined in claim 6 wherein said control effect generating device comprises a relay having at least one set of contacts actuated by the discharge current produced by said trip capacitor.

9. A fault indicator as defined in claim 5 wherein said charge circuit means provide recurring unidirectional current pulses, and the time constant of said charge transfer circuit formed by said trip and trip inhibit capacitors and said resistor sufficiently exceed the pulse period of said charge current pulses such that said trip capacitor remains substantially fully charged between said pulses.

10. A fault indicator as defined in claim 4 wherein said voltage limiting means comprise a diode forward-biased to said charging current.

11. A fault indicator as defined in claim 1 wherein said control effect generating device comprises an electrically actuated indicator flag.

12. A fault indicator for producing a control effect in response to the occurrence of a fault current in a monitored conductor, comprising:

status indicating means having reset-indicating and fault-indicating states;

trip circuit means including a trip capacitor for utilizing the charge stored in said trip capacitor to condition said status indicating means to said fault-indicating state in response to the occurrence of a fault current in the electrical conductor;

a trip inhibit capacitor;

charge circuit means including a rectifier circuit coupled to the monitored conductor for developing a charge current for charging said capacitors, said trip and trip inhibit capacitors being connected in series across the output of said rectifier circuit to receive said charge current;

voltage limiting means comprising a diode forward-biased to said charge current and connected across said trip inhibit capacitor for limiting the voltage developed thereacross by said charge current to a predetermined nominal level;

circuit means including a resistor connected between the unconnected terminals of said capacitors, said circuit means being operable upon interruption of said charge current for establishing current flow between said trip capacitor and said trip inhibit capacitor, the terminal voltage across said trip inhibit capacitor progressively increasing from said predetermined nominal level with said current flow; and

trigger circuit means responsive to the voltage across said trip inhibit capacitor increasing beyond a predetermined threshold level for discharging said trip capacitor to render said trip circuit means inoperative and the fault indicator non-responsive to inrush current in the conductor.

13. A fault indicator as defined in claim 12 wherein the capacitance of said trip inhibit capacitor is substantially less than the capacitance of trip first capacitor.

14. A fault indicator as defined in claim 12 wherein said trigger circuit means comprise a control effect generating device and a transistor, said transistor having a first main electrode connected to the connected terminal of said capacitors, and a second main electrode connected through said generating device to the non-connected terminal of said trip capacitor, and a gate electrode connected to the non-connected terminal of said trip inhibit capacitor, and further having between said gate electrode and said first main electrode a threshold voltage level above which conduction is initiated between said main electrodes.

15. A fault indicator as defined in claim 14 wherein said transistor is a field effect transistor.

16. A fault indicator as defined in claim 12 wherein said charge circuit means provide recurring unidirectional current pulses, and the time constant of said charge transfer circuit formed by said trip and trip inhibit capacitors and said resistor sufficiently exceed the pulse period of said charge current pulses such that said trip capacitor remains substantially fully charged between said pulses.

17. A fault indicator as defined in claim 12 wherein said control effect generating device comprises an electrically actuated indicator flag.

18. A fault indicator for producing a control effect in response to the occurrence of a fault current in a monitored conductor, comprising:

status indicating means having reset-indicating and fault-indicating states;

trip circuit means including a trip capacitor for utilizing the charge stored in said trip capacitor to condition said status indicating means to said fault-indicating state in response to the occurrence of a fault current in the electrical conductor;

a trip inhibit capacitor;

charge current means including a rectifier circuit coupled to the monitored conductor for developing a charge current for charging said capacitors, said capacitors being connected in series across the output of said rectifier circuit to receive said charge current;

voltage limiting means comprising a diode forward-biased to said charge current and connected across said trip inhibit capacitor for limiting the voltage developed thereacross by said charge current to a predetermined nominal level; and

trigger circuit means including a field effect transistor having a first main electrode connected to the connected terminals of said capacitors, and a second main electrode connected througth a discharge current limiting resistor to the non-connected terminal of said trip capacitor, and a gate electrode connected to the non-connected terminal of said trip inhibit capacitor, and further having between said gate electrode and said first main electrode a threshold voltage level above which conduction is initiated between said main electrodes, for discharging said trip capacitor through said discharge current limiting resistor to render said trip circuit means inoperative and the fault indicator non-responsive to inrush current in the conductor.

19. A fault indicator as defined in claim 18 wherein the capacitance of said trip inhibit capacitor is substantially less than the capacitance of said trip capacitor.

20. A fault indicator as defined in claim 18 wherein said charge circuit means provide recurring unidirectional current pulses, and the time constant of said delay circuit sufficiently exceeds the pulse period of said charge current pulses such that said trip capacitor remains substantially fully charged between said pulses.