Cache memory architecture for microcomputer speed-up board

• US 4,794,523 A
• Filed: 09/30/1985
• Issued: 12/27/1988
• Est. Priority Date: 09/30/1985
• Status: Expired due to Fees

• Current Assignee: Loudware Incorporated
• Original Assignee: Loudware Incorporated
• Inventors: McCaslin, Robert, Adan, Manolito, Meadows, Steven
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US06/782,664
• Time in Patent Office: 1,184 Days
• Field of Search: 364/200, 364/900
• US Class Current: 713/100
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

A method and apparatus for enhancing the speed of operation of a computer consists of providing a cache memory which is faster than the computer'"'"'s main memory, disabling the computer'"'"'s main microprocessor, and replacing it with a microprocessor with a faster clock cycle time. A portion of the program stored in the main memory is stored in the cache memory. The addresses of the portion of the main memory stored in the cache memory are noted in a tag RAM. Upon each addressing sequence during the execution of a program, the tag RAM is examined to determine if the addressed located is stored in the cache memory. If the stored location is identified in the tag RAM, it is retrieved from the cache memory at high-speed. Otherwise, the data in the address location is retrieved from main memory at a slower speed and written into the cache memory so that subsequent accesses may be made at high-speed.

Claims

1. A method for enhancing the speed of operation of a computer having a plurality of devices including a first microprocessor coupled to a main memory via an address bus, said computer being designed to operate at a first clock cycle time, comprising the steps of:

providing a cache memory having a faster access time than an access time of said main memory used by said computer;

permanently disabling or disconnecting said first microprocessor on or before power-up;

producing a second clock having a faster cycle time than said first clock cycle time;

providing a second microprocessor operating at said second clock cycle time;

storing a portion of the data of said main memory in said cache memory;

intercepting an addressing of a location in said main memory on said address bus by said fast microprocessor;

producing a signal designating one of a plurality of banks of said main memory in response to the addressing of a location in said main memory by said second microprocessor, each of said banks using the same addresses from said second microprocessor;

determining, in response to said addressing of a location in said main memory, whether the data of said location is stored in said cache memory;

retrieving said data for said fast microprocessor from said cache memory at said faster access time if said data are determined to be in said cache memory; and

communicating with said plurality of devices, excluding said first microprocessor, at said first clock cycle time.

2. The method of claim 1 wherein said determining step comprises the steps of:

storing, in a tag memory, a first portion of each of said main memory addresses for data also stored in said cache memory, said data being stored in said cache memory at a location in said cache memory corresponding to a second portion of said main memory address; and

comparing a first portion of a current address to said address first portion stored in said tag memory.

3. The method of claim 1 wherein said data is stored in said cache memory upon a first request for said data.

4. The method of claim 3 further comprising the step of eliminating an earlier byte of data stored in a cache memory location upon a request for a byte of data after said cache memory location is filled.

5. The method of claim 1 wherein said disabling step comprises providing a signal to a direct memory access line of said computer.

6. The method of claim 1 further comprising the steps of:

decoding an address to determine the location of said address; and

providing a clock speed for said second microprocessor compatible with said location.

7. The method of claim 1 further comprising the steps of:

storing an element of data to be written into said main memory in a buffer during a clock cycle corresponding to said faster access time; and

subsequently writing said element of data into said main memory during a slower clock cycle independent of said faster access clock cycle.

8. A method for enhancing the speed of operation of a computer having a plurality of devices including a first microprocessor coupled to a main memory via an address bus, said computer being designed to operate at a first clock cycle time, comprising the steps of:

providing a cache memory having a faster access time than an access time of said main memory used by said computer;

permanently disabling or disconnecting said first microprocessor on or before power-up;

producing a second clock having a faster cycle time than said first clock cycle time;

providing a second microprocessor operating at said second clock cycle time;

storing a portion of the data of said main memory in said cache memory;

intercepting an addressing of a location in said main memory on said address bus by said fast microprocessor;

producing a signal designating one of a plurality of banks of said main memory in response to the addressing of a location in said main memory by said second microprocessor, each of said banks using the same addresses from said second microprocessor;

storing, in a tag memory, a first portion of each of the main memory addresses for data also stored in said cache memory, said data being stored in said cache memory at a location in said cache memory corresponding to a second portion of said main memory address;

comparing a first portion of a current address to said address first portion stored in said tag memory;

retrieving said data from said cache memory if said compared addresses are identical; and

communicating with said plurality of devices, excluding said first microprocessor, at said first clock cycle time.

9. An apparatus for enhancing the speed of operation of a computer having a plurality of devices including a first microprocessor and a main memory, said computer being designed to operate at a first clock cycle time, comprising:

means for coupling said apparatus to address and data lines coupled to said first microprocessor and permanently disabling said first microprocessor on or before power-up;

means for communicating with said plurality of devices, excluding said first microprocessor, at said first clock cycle time;

means for producing a second clock having a faster cycle time than said first clock cycle time;

a cache memory having a faster access time than an access time of said main memory used by said computer;

a second microprocessor operating at said second clock cycle time;

means for storing a portion of the data of said main memory in said cache memory;

means for producing a signal designating one of a plurality of banks of said main memory in response to the addressing of a location in said main memory by said second microprocessor, each of said banks using the same addresses from said second microprocessor;

means for determining, in response to the addressing of a location in said main memory by said second microprocessor, whether the data of said location is stored in said cache memory; and

means for retrieving said data for said second microprocessor from said cache memory using said second clock if said data are determined to be in said cache memory.

10. The apparatus of claim 9 wherein said means for determining comprises:

a tag memory;

means for storing in said tag memory a first portion of each of said main memory addresses for data stored in said cache memory at a location in said cache memory corresponding to a second portion of said main memory address; and

means for comparing a first portion of a current address to said address first portion stored in said tag memory.

11. The apparatus of claim 9 wherein said data is stored in said cache memory upon a first request for said data.

12. The apparatus of claim 11 further comprising means for eliminating an earlier byte of data stored in a cache memory location upon a request for a byte of data from said main memory after said cache memory location is filled.

13. The apparatus of claim 9 wherein said disabling means comprises means for providing a signal to a direct memory access line of said first microprocessor.

14. The apparatus of claim 9 further comprising:

means for decoding an address from said second microprocessor to determine the location of said address; and

means for providing an addressing sequence clock speed for said second microprocessor compatible with said location.

15. The apparatus of claim 9 further comprising:

a buffer for storing an element of data to be written into said main memory during a clock cycle corresponding to said faster access time; and

means for subsequently writing said element of data into said main memory during a slower clock cycle.

16. An add-on apparatus for enhancing the speed of operation of a computer having a plurality of devices including a first microprocessor and a main memory, said computer being designed to operate at a first clock cycle time, comprising:

means for coupling said apparatus to a first address bus and first data bus coupled to said first microprocessor and permanently disabling said first microprocessor on or before power-up;

means for communicating with said plurality of devices, excluding said first microprocessor, at said first clock cycle time;

means for producing a second clock having a faster cycle time than said first clock cycle time;

a second microprocessor operating at said second clock cycle time;

a cache memory having a faster access time than an access time of said main memory of said computer, said cache memory being smaller than said main memory;

a tag memory for storing a first portion of each main memory address for data also stored in said cache memory, said first address portion being stored in said tag memory at an address corresponding to a second portion of said main memory address;

a comparator for comparing a first portion of a current address with a first address portion stored in said tag memory;

control means for retrieving data for said second microprocessor from said cache memory at said faster access time responsive to said comparator;

a fast data bus, internal to said add-on apparatus, coupled to said second microprocessor and said cache memory;

a fast address bus, internal to said add-on apparatus, coupled to said second microprocessor, said tag memory and said comparator;

means for producing a signal designating one of a plurality of banks of said main memory in response to the addressing of a location in said main memory by said second microprocessor, each of said banks using the same addresses from said second microprocessor;

a first buffer means for coupling said fast data bus to said first data bus of said first microprocessor; and

a second buffer means for coupling said fast address bus to said first address bus of said first microprocessor.