Content addressable semiconductor memory arrays

• US 4,794,559 A
• Filed: 07/05/1984
• Issued: 12/27/1988
• Est. Priority Date: 07/05/1984
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Greenberger, Alan J.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/628,165
• Time in Patent Office: 1,636 Days
• Field of Search: 365/49, 365/189, 365/230, 365/233, 365/201, 340/796, 371/21
• US Class Current: 711/105
• CPC Class Codes: G06F 16/90335 Query processing
• CPC Class Codes: G06F 16/90339 by using parallel associative memories or content-addressable memories
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements

Abstract

A semiconductor memory circuit is arranged with an ordinary crosspoint row-column array of dynamic capacitor memory storage cells. Word serial content addressing is enabled by adding a separate combinational logic device, only one such device for each entire column bit line, typically comprising a comparator feeding a NAND gate to which masking data can be supplied.

Claims

1. A semiconductor memory circuit comprising:

(a) a crosspoint bit line-wordline array of dynamic semiconductor memory cells for storing data, a separate complementary bit line for each bit line, a plurality of cells on each bit line and a plurality of cells on each complementary bit line;

(b) means for separately activating each of the wordlines;

(c) a single equality output line which is connected to each of the bit lines through a separate logic device, one and only one such device for each bit line plus the complementary bit line; and

(d) means, responsive to the data stored in the cells, for identifying whether any wordline which is being activated stores a word portion that matches a test word portion, including means for developing on the equality output line a logic output state representing whether or not the wordline contains a word portion that matches the test word portion.

2. The array of claim 1 in which each of the cells consists essentially of a separate capacitor and a separate transistor through which the capacitor is connected to the corresponding bit line, a control terminal of the transistor being connected to the corresponding wordline.

3. The array of claim 1 in which each such logic device is combinational logic containing at most two single-bit comparators for comparing the logic level of a corresponding bit of the test word portion with the logic level of the corresponding bit line or of the corresponding complementary bit line.

4. The array of claim 3 in which each of the cells consists essentially of a separate capacitor and a separate transistor through which the capacitor is connected to the corresponding bit line, a control terminal of the transistor being connected to the corresponding wordline.

5. A semiconductor integrated circuit arrangement comprising:

(a) a crosspoint random access row-column array of semiconductor dynamic binary memory storage cells, the array having a plurality of column bit access lines, a separate complementary bit line for each of the bit access lines, a plurality of row word access lines, a separate such dynamic binary memory storage cell connected across each crosspoint of one of the word lines and one of the bit access lines, and a separate such cell connected across each crosspoint of one of the word lines and one of the complementary bit lines, whereby during refresh operation, when a given word access line is activated, each column bit access line is supplied with a separate memory bit signal representing the bit and only the bit stored in the storage cell located at the crosspoint of that column bit access line or of its complementary bit line and the given wordline;

(b) an output equality line;

(c) separate sense-refreshed means connected across each such column bit access line and its complementary bit line;

(d) a separate combinational logic device associated with each such column bit line together with its complementary bit line, one and only one such device for each such bit line plus its complementary bit line, each such logic device connected for receiving;

(1) a separate test bit signal corresponding to the associated bit line,

(2) the complement of such test bit signal,

(3) a separate unmasking bit signal corresponding to the associated bit line,

(4) the corresponding memory bit signal thus supplied to the associated bit access line during the refresh operation, and

(5) the complement of such memory signal; and

each such combinational logic device connected for delivering an output signal to the output equality line which is low only if, when the unmasking bit is high, the test bit does not match the memory bit signal on the associated column bit line.

6. The circuit of claim 5 in which each such combinational logic includes at most two single-bit comparators for comparing the logic levels of the test bit and its associated bit line or its associated complementary bit line.

7. A semiconductor integrated memory circuit comprising:

(a) a plurality of memory blocks, each memory block being a crosspoint array in accordance with the array of paragraph (a) of claim 5, each of the plurality of word access lines for each block being an extension of the corresponding word access line of all the other blocks;

(b) a plurality of separate output equality lines equal to the number of memory blocks, each such equality line being associated with a different one of the memory blocks; and

(c) a resolver, to which all the equality lines are connected, for detecting and registering the resulting signal level on each of the equality lines.

8. A semiconductor integrated circuit arrangement comprising:

(a) a crosspoint random access row-column array of semiconductor dynamic capacitor binary memory storage cells, the array having a plurality of column bit access lines, a separate complementary bit line for each of the bit access lines, a plurality of row word access lines, and a separate such dynamic binary storage cell connected across each crosspoint of a word line and a bit access line, and another separate such cell connected across each crosspoint of a word line and a complementary bit line, whereby during refresh operation, when a given word access line is activated, each column bit access line is supplied with a separate memory bit signal representing the bit and only the bit stored in the storage cell located at the crosspoint of that column bit line or its complementary bit line and the given wordline;

(b) an output equality line;

(c) separate sense-refresh means connected across each such column bit line access line and its complementary bit line;

(d) a separate combinational logic device associated with each such column bit line and its complementary bit line, one and only one such device for each such column bit access line, each such logic connected for receiving;

(1) a separate test bit signal corresponding to the associated bit line,

(2) the complement of such test bit signal,

(3) a separate unmasking bit signal corresponding to the associated bit line,

(4) the corresponding memory bit signal thus supplied to the associated bit line during the refresh operation, and

(5) the complement of such memory signal; and

each such combinational logic connected for delivering an output signal to the output equality line which is low if and only if, when the unmasking bit is high, the test bit does not match the memory bit signal on the associated column bit line.

9. The circuit of claim 8 in which each combinational logic device consists essentially of:

a first transistor whose gate terminal is connected for receiving the unmasking bit signal and whose source-drain path is connected in series with two parallel branches,

one of the branches consisting essentially of second and third transistors whose source-drain paths are connected in series with each other, the gate terminal of the second transistor being connected for receiving the memory bit signal, and the gate terminal of the third transistor being connected for receiving the complement of the test bit signal,

the other of the branches consisting of fourth and fifth transistors whose source-drain paths are connected in series with each other, the gate terminal of the fourth transistor being connected for receiving the complement of the memory bit signal, and the gate terminal of the fifth transistor being connected for receiving the test bit signal.