Memory device equipped with a RAS circuit

• US 4,794,597 A
• Filed: 12/23/1986
• Issued: 12/27/1988
• Est. Priority Date: 03/28/1986
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kojima, Tooru, Ooba, Kunio
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US06/945,530
• Time in Patent Office: 735 Days
• Field of Search: 371/3, 371/13, 371/38
• US Class Current: 714/703
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

In a storage unit equipped with a Reliablity, Availability and Serviceability (RAS) circuit, including a memory unit constructed of, e.g., a dynamic random access memory (DRAM) unit, for storing data with an error coding code (ECC), and an ECC unit constructed of e.g., an ECC checking circuit, for correcting a 1-bit error and detecting a 1-bit error, or more than 2-bit error contained in the data read from the memory unit, an ECC diagnostic unit is connected between said memory unit and said ECC unit, and an error made concerning the memory unit and ECC unit is diagnosed by the ECC diagnostic unit by selectively inverting the data read from the memory unit into diagnostic data during the checking operation of the ECC units to diagnose proper operation of the ECC unit and detect erros.

Claims

1. A storage device equipped with a reliability, availability and serviceability (referred to as "RAS") circuit, having a memory unit for storing data to which an error-correcting code (referred to as "ECC") has been applied, and an ECC checking circuit for detecting 1-bit, or more than 2-bit error contained in data read from the memory unit, characterized by comprising:

a diagnostic data inverting unit connected between said memory unit and said ECC checking circuit for diagnosing an error mode with respect to said ECC checking circuit and said memory unit by inverting into diagnostic data the data being read from said memory unit during the checking operation by said ECC checking circuit wherein said diagnostic data inverting unit includes;

a test switch connected to said memory unit;

a data input latch circuit for latching said data in response to a latch signal;

a latch-output-validity selecting gate connected to said data input latch circuit for selectively controlling validity and invalidity of the output of asid data input latch circuit; and

an exclusive OR circuit connected to receive a mode input and the output of said latch circuit for generating an OR-gated signal between the mode input and the data input.

2. A storage device equipped with a RAS circuit, including a memory unit for data with ECC, and an ECC checking circuit for detecting an error contained in the data read from said memory unit, and a memory unit/ECC checking circuit control unit for controlling said memory unit and said ECC checking circuit, characterized in that

said memory unit is constructed of a dynamic random access memory (referred to as "DRAM") element;

said DRAM memory unit delivers a refreshing status signal, by which reading operation is carried out during refreshing operation, to said memory unit/ECC checking circuit control unit;

when a 1-bit error is detected by said ECC checking circuit from output data of said DRAM memory unit, correcting data is rewritten into corresponding address of said DRAM element, and only said 1-bit error is corrected during the reading operation other than said refreshing operation; and

an operating cycle control circuit for the storage device is included in said memory unit/ECC checking circuit control unit, said refreshing status signal of said memory unit and a 1-bit error detection signal generated from said ECC checking circuit being input via an AND circuit into said operating cycle control circuit.

3. A storage device as claimed in claim 2, wherein said memory unit/ECC checking circuit control unit includes, other than said AND circuit and said operating cycle control circuit, an OR circuit for OR-gating the output of said AND circuit and a memory write signal during the writing operation on said DRAM memory unit to generate a write signal to said DRAM memory unit.

4. A storage device equipped with a RAS circuit comprising:

a data bus for transmitting various data within the storage device;

a memory unit for storing data with ECC;

an ECC unit connected to said data bus via a 1-bit error register and a 2-bit and more bit error status signal generator, for correcting the errors in case of a 1-bit error and detecting the errors occurring in the storage device by selectively inverting 1-bit or more than 2-bit data of the output data of said memory unit to diagnose proper operation of said ECC unit and detect errors;

an ECC diagnostic unit connected between said ECC unit and said memory unit, for diagnosing extraordinary outputs of said memory units by receiving the output data of said memory unit and for supplying results of said diagnosis to said ECC unit; and

an ECC function/memory element diagnostic unit connected to said data bus, for diagnosing whether or not said ECC function of said ECC unit is malfunctioning and whether or not said memory element constituting said memory unit has failed by confirming various functions of the 1-bit error correction by said ECC unit, of the 2-bit error detection, of Hamming code generation and of syndrome code generation based upon the result of the diagnosis by said ECC diagnostic unit.

5. A storage device as claimed in claim 4, wherein said ECC function/memory element diagnostic unit includes:

information reading means for reading information of said 1-bit error register connected between said ECC unit and said bus;

measuring means connected to said 1-bit error register for accumulating the occurrence number of said 1-bit errors and for measuring system operation time;

calculating means for calculating a failure rate in the system

means for providing a preset software error rate of said memory element; and

means for comparing the failure rate calculated by said calculation means with the preset software error rate of said memory element, whereby the system is diagnosed as a normal condition in case that the failure rate is smaller than the software error rate, whereas a judgement can be made whether said ECC unit is malfunctioning, or the hardware of said memory element has failed by diagnosing the function of said ECC unit by means of said ECC diagnostic unit when the failure rate is greater than the software error rate.

6. A storage device as claimed in claim 4, wherein ECC function/memory element diagnostic unit can diagnose whether the ECC unit is malfunctioning, or the memory element has failed under the condition that when 2-bit and more than 2-bit errors occur from said ECC unit, the signal from the 2-bit error status signal generator is received by said ECC function/memory element diagnostic unit.

7. A storage device as claimed in claim 4, wherein a 1-bit error counter is connected, instead of said 1-bit error register, between said data bus and said ECC unit.

8. A storage device as claimed in claim 4, wherein a 2-bit and more bit error register is connected, instead of said 2-bit and more bit status signal generator, between said data bus and said ECC unit.