Integrated analog-to-digital converter

• US 4,796,004 A
• Filed: 02/14/1986
• Issued: 01/03/1989
• Est. Priority Date: 02/14/1986
• Status: Expired due to Term

• Current Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: Staley, Peter, Coyne, David, Rich, David
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/829,624
• Time in Patent Office: 1,054 Days
• Field of Search: 340/347 AD, 364/724, 364/768, 375/27, 375/28, 375/29, 375/33
• US Class Current: 341/143
• CPC Class Codes: G06F 2207/388 Skewing
• CPC Class Codes: G06F 7/5095 word-serial, i.e. with an accumulator-register
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 5/15066 using bistable devices H03K5/15093 takes precedence
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
• CPC Class Codes: H03M 3/462 Details relating to the decimation process decimation filters in general H03H17/0416, H03H17/0621

Abstract

A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impulse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stages operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

Claims

1. An integrated analog-to-digital converter comprisingg a second order delta sigma modulator for generating a single bit per time output signal and a decimator for reducing the sampling rate of said modular output signal by a rational number and generating a pulse code modulated word, said modulated comprising first and second summation means, each having first and second inputs and an output, first and second filter means, bistable means, and inverter means, said first input of said first summation means being operably connected to receive the analog input, the input of said first filter means being operably connected to the output of said first summation means, said fist input of said second summation means being operably connected to the output of said first filter means, the input of said second filter means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second filter means, said inverter means being operably connected between the output of said bistable means and said second input of said second summation means, said output of said bistable means being operably connected to said second input of said first summation means and to form the modulator output, each of said filter means comprising CMOS push/pull amplification means.

2. The converter of claim 1, wherein said decimator comprises a finite impulse response filter and a sub-sampler.

3. The converter of claim 2, wherein said filter and sub-sampler comprise partial coefficient generator means and an accumulator.

4. An integrated analog to digital converter comprising a second order delta sigma modulator and a decimator, said modulator comprising first and second summation means, each having first and second inputs and an output, first and second filter means, bistable means, and inverter means, said first input of said first summation means being operably connected to receive the analog input, the input of said first filter means being operably connected to the output of said first summation means, said first input of said second summation means being operably connected to the output of said first filter means, the input of said second filter means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second filter means, said inverter means being operably connected between the output of said bistable means and said second input of said second summation means, said output of said bistable means being operably connected to said second input of said first summation means and to form the modulator output, each of said filter means comprising CMOS push/pull amplification means, said decimator comprising a finite impulse filter and a subsampler, said filter and said subsampler comprising partial coefficient generator means and an accumulator, the converter further comprising means for generating a plurality of ordered timed pulse trains, each pulse trains having a frequency which is a given fraction of the frequency of the prior timing signal in order and wherein said partial coefficient generator means comprises means for receiving said modulator output, means for delaying said modulator output, a plurality of selector logic means, each of said logic means receiving a different one of said pulse trains, said modulator input and said delayed modulator input, and generating one bit of a parallel output word.

5. The converter of claim 4, wherein each of said logic means comprises means for forming an output to be at the same state as the state of the received pulse train, if the modulator output is in a high stage, to be the complement of the state of the received pulse train, if the delayed modulator output is in a high state, to be a high state if both the modulator output and the delayed modulator output are in the high state, and to be a low state if both the modulator output and the delayed modulator output are in the low state.

6. The converter of claim 5, wherein said accumulator means comprises means for delaying each bit of said parallel output word by an interval which is a function of the position of the bit in the output word.

7. The converter of claim 6, wherein said accumulator comprises a plurality of stages, wherein each of said stages comprises adder means having first and second data inputs, a clock input, a sum output and a carry output, said first data input of each of said adder means receiving a different bit from the output of said delaying means, means for operably connecting said second data input of each adder means with said sum output thereof and means for operably connecting said clock input to said carry output of the adder means of said preceding stage.

8. The converter of claim 7, wherein said means for connecting said second data input of each adder means to said sum output thereof comprises sum output delay means.

9. The converter of claim 8, wherein said means for connecting said clock input of each adder means to said carry output of said adder means of said preceding stage comprises carry output delay means.

10. The converter of claim 9, wherein said accumulator further comprises a multiplexer comprising said given number of shift register stages respectively corresponding with said stages, and connected in tandem, each of said shift register stages having an output, each of said outputs being operably connected to said sum output delay means of the corresponding stage.

11. The converter of claim 10, wherein said multiplexer further comprises means for inverting the output of the last shift register stage.