Integrated analog-to-digital converter
First Claim
1. An integrated analog-to-digital converter comprisingg a second order delta sigma modulator for generating a single bit per time output signal and a decimator for reducing the sampling rate of said modular output signal by a rational number and generating a pulse code modulated word, said modulated comprising first and second summation means, each having first and second inputs and an output, first and second filter means, bistable means, and inverter means, said first input of said first summation means being operably connected to receive the analog input, the input of said first filter means being operably connected to the output of said first summation means, said fist input of said second summation means being operably connected to the output of said first filter means, the input of said second filter means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second filter means, said inverter means being operably connected between the output of said bistable means and said second input of said second summation means, said output of said bistable means being operably connected to said second input of said first summation means and to form the modulator output, each of said filter means comprising CMOS push/pull amplification means.
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Abstract
A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impulse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stages operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.
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Citations
11 Claims
- 1. An integrated analog-to-digital converter comprisingg a second order delta sigma modulator for generating a single bit per time output signal and a decimator for reducing the sampling rate of said modular output signal by a rational number and generating a pulse code modulated word, said modulated comprising first and second summation means, each having first and second inputs and an output, first and second filter means, bistable means, and inverter means, said first input of said first summation means being operably connected to receive the analog input, the input of said first filter means being operably connected to the output of said first summation means, said fist input of said second summation means being operably connected to the output of said first filter means, the input of said second filter means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second filter means, said inverter means being operably connected between the output of said bistable means and said second input of said second summation means, said output of said bistable means being operably connected to said second input of said first summation means and to form the modulator output, each of said filter means comprising CMOS push/pull amplification means.
- 4. An integrated analog to digital converter comprising a second order delta sigma modulator and a decimator, said modulator comprising first and second summation means, each having first and second inputs and an output, first and second filter means, bistable means, and inverter means, said first input of said first summation means being operably connected to receive the analog input, the input of said first filter means being operably connected to the output of said first summation means, said first input of said second summation means being operably connected to the output of said first filter means, the input of said second filter means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second filter means, said inverter means being operably connected between the output of said bistable means and said second input of said second summation means, said output of said bistable means being operably connected to said second input of said first summation means and to form the modulator output, each of said filter means comprising CMOS push/pull amplification means, said decimator comprising a finite impulse filter and a subsampler, said filter and said subsampler comprising partial coefficient generator means and an accumulator, the converter further comprising means for generating a plurality of ordered timed pulse trains, each pulse trains having a frequency which is a given fraction of the frequency of the prior timing signal in order and wherein said partial coefficient generator means comprises means for receiving said modulator output, means for delaying said modulator output, a plurality of selector logic means, each of said logic means receiving a different one of said pulse trains, said modulator input and said delayed modulator input, and generating one bit of a parallel output word.
Specification