Method of fabricating a high density masked programmable read-only memory

• US 4,796,074 A
• Filed: 04/27/1987
• Issued: 01/03/1989
• Est. Priority Date: 04/27/1987
• Status: Expired due to Fees

• Current Assignee: ICC El Camino Del Mar San Francisco California 95121
• Original Assignee: Instant Circuit Corporation
• Inventors: Roesner, Bruce B.
• Primary Examiner(s): Carroll, J.
• Assistant Examiner(s): NGO, NGAN V
• Application Number:
  US07/042,682
• Time in Patent Office: 617 Days
• Field of Search: 357/15, 357/59 A, 357/59 F, 357/59 I, 357/59 K, 357/40, 357/51, 357/47, 365/100, 365/105, 365/103
• US Class Current: 257/476
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration

Abstract

The word line pitch within a read-only memory is decreased, thereby increasing the cell density within the memory, without imposing any additional or stricter spacing rules or fabrication techniques utilized in the manufacture of the read-only memory integrated circuit chip. The read-only memory is comprised of a plurality of memory cells. A two-dimensional semiconductor diode layer is laid down on a plurality of word lines which have previously been disposed upon a semiconductor supporting substrate. The semiconductor diode layer is disposed on the plurality of word lines without regard to any alignment criteria. A programmable material is inlaid on the Schottky diodes and a plurality of bit lines laid upon the programmable material. The bit lines and word lines are orthogonally disposed with respect to the Schottky diodes so that each diode is uniquely addressed by one word line and one bit line. The programmable material may be laid upon the Schottky diode as a two-dimensional layer or as a plurality of strips or paths without regard to any alignment criteria. Because a single alignment is required in each of two orthogonal dimensions between the word line and the Schottky diode in one dimension, or the bit line and Schottky diode in another dimension, the center-to-center word line or bit line pitch is reduced to four microns and utilizing a fabrication methodology based a two-micron rule.

Claims

1. An electrical programmable read-only memory comprising:

a semiconductor substrate;

a plurality of conductive word lines disposed on said substrate;

a first semiconductor material having a polycrystalline grain structure disposed on and between said plurality of word lines and on said substrate, said first semiconductor material having a sufficiently high lateral resistivity to avoid significant electrical conduction between adjacent ones of said conductive word lines, thereby avoiding limitations on the closeness of spacing of said conductive word lines to each other on said substrate, which limitations would have otherwise been encountered if said first semiconductor material were selectively disposed on said word lines;

an insulating layer disposed upon said first semiconductor material, said insulating layer having a plurality of apertures defined therethrough exposing portions of said first semiconductor material, each of said apertures defined in said insulating layer being approximately aligned with one of said word lines disposed beneath said aperture and said first semiconductor material;

a metallic compound in contact with said first semiconductor material forming a plurality of Schottky diodes therewith, said metallic compound being disposed in the form of a two-dimensional layer within each of said apertures in said insulating layer, a Schottky diode being formed in each of said plurality of apertures;

a second semiconductor layer disposed at least within said apertures in electrical contact with said metallic compound, said second semiconductor layer composed of semiconductor material having a first and second electrical state, said semiconductor material of said second semiconductor layer being electrically and permanently configured to said second electrical state from said first electrical state upon application of a threshold signal to said second semiconductor material; and

a plurality of conductive bit lines disposed on said second semiconductor layer and aligned at least with said metallic compound underlying said second semiconductor layer,

whereby cell densities in said memory is increased and having a decreased bit line and word line pitch without any increase in fabrication and alignment tolerances by which said memory is constructed.

2. The memory of claim 1 wherein said second semiconductor layer is disposed on said insulating layer and said metallic compound as a two lateral dimensional layer having an area substantially larger than at least one memory cell and disposed thereon without regard to alignment to structure underlying said metallic compound.

3. The memory of claim 1 wherein said second semiconductor layer is disposed on said underlying metallic compound in the form of a plurality of two lateral dimensional pads each pad being disposed at least in part in said aperture defined within said insulating layer and in contact at least in part with said metallic compound.

4. The memory of claim 1 wherein said first electrical state of said second semiconductor layer is a state characterized by high vertical electrical resistivity and wherein said second electrical state is a state characterized by low vertical electrical resistivity, said signal, which irreversibly configures said second semiconductor material from said first electrical state to said second electrical state, being a voltage exceeding a predetermined threshold voltage applied across at least a portion of said second semiconductor material, only that portion being subjected to said threshold voltage being configured from said first electrical state to said second electrical state, the remaining portion of said second semiconductor material, which is not exposed to said threshold voltage, remaining in said first electrical state of high vertical resistivity.

5. The memory of claim 2 wherein said first electrical state of said second semiconductor layer is a state characterized by high vertical electrical resistivity and wherein said second electrical state is a state characterized by low vertical electrical resistivity, said signal, which irreversibly configures said second semiconductor material from said first electrical state to said second electrical state, being a voltage exceeding a predetermined threshold voltage applied across at least a portion of said second semiconductor material, only that portion being subjected to said threshold voltage being configured from said first electrical state to said second electrical state, the remaining portion of said second semiconductor material, which is not exposed to said threshold voltage, remaining in said first electrical state of high vertical resistivity.

6. The memory of claim 5 wherein said second semiconductor material consists essentially of a single element semiconductor selected from a group of silicon, germanium, carbon and alpha-tin having a crystalline grain size which is smaller than that of said first semiconductor material and having a concentration of dopant atoms of less than 10¹⁷ per cubic centimeter.

7. The memory of claim 6 wherein said second semiconductor material is comprised of relatively smaller grain size silicon than said first semiconductor material, said first semiconductor material being subjected to temperatures of over 600 degrees C. whereas said second semiconductor material is subjected to temperatures of only less than 600 degrees C. to achieve its relatively smaller grain sizes as compared to said first semiconductor material.

8. An electrical programmable read-only memory having memory cells in an insulating layer which overlies a semiconductor substrate comprising:

a semiconductor substrate;

a plurality of conductive word lines disposed on said substrate;

a first semiconductor layer composed of semiconductor material having a polycrystalline grain structure formed as a two lateral dimensional layer on and between said plurality of word lines and on said substrate without selective delineation of said first semiconductor layer with respect to said word lines, said first semiconductor material having a sufficiently high lateral resistivity to avoid significant electrical conduction between adjacent ones of said conductive word lines, thereby avoiding limitations on the closeness of spacing of said conductive word lines to each other on said substrate which limitations would have otherwise been encountered if said first semiconductor layer were selectively disposed on said word lines;

an insulating layer disposed upon said first semiconductor layer, said insulating layer having a plurality of apertures defined therethrough exposing portions of said first semiconductor layer, each of said apertures defined in said insulating layer being approximately aligned with one of said word lines disposed beneath said aperture and said first semiconductor layer;

a metallic compound in contact with said first semiconductor layer forming a plurality of Schottky diodes therewith, said metallic compound being disposed in the form of a two lateral dimensional layer within each of said apertures in said insulating layer, a Schottky diode being formed in each of said plurality of apertures;

a second semiconductor layer disposed at least within said apertures in electrical contact with said metallic compound, said second semiconductor layer composed of semiconductor material having a first and second electrical state, said semiconductor material being electrically and permanently configured to said second electrical state from said first electrical state upon application of a threshold signal to said semiconductor material of said second semiconductor layer; and

a plurality of conductive bit lines disposed on said second semiconductor layer and aligned at least with said metallic compound underlying said second semiconductor layer,

whereby cell densities in said memory are increased and having a decreased bit line and word line pitch without any increase in fabrication and alignment tolerances by which said memory is constructed.

9. An electrical programmable read-only memory comprising:

a semiconductor substrate;

a plurality of conductive word lines disposed on said substrate;

a first semiconductor layer composed of semiconductor material having a polycrystalline grain structure formed as a two lateral dimensional layer on and between said plurality of word lines and on said substrate without registration of any kind with respect to said underlying word lines, said first semiconductor material having a sufficiently high lateral resistivity to avoid significant electrical conduction between adjacent ones of said conductive word lines, thereby avoiding limitations on the closeness of spacing of said conductive word lines to each other on said substrate which limitations would have otherwise been encountered if said first semiconductor layer were selectively disposed on said word lines;

an insulating layer disposed upon said first semiconductor layer, said insulating layer having a plurality of apertures defined therethrough exposing portions of said first semiconductor layer, each of said apertures defined in said insulating layer being approximately aligned with one of said word lines disposed beneath said aperture and said first semiconductor layer;

a metallic compound in contact with said first semiconductor layer forming a plurality of Schottky diodes therewith, said metallic compound being disposed in the form of a two lateral dimensional layer within each of said apertures in said insulating layer, a Schottky diode being formed in each of said plurality of apertures;

a second semiconductor layer disposed at least within said apertures in electrical contact with said metallic compound, said second semiconductor layer composed of semiconductor material having a first high resistivity and second low resistivity electrical state, selected portions of said semiconductor material of said second semiconductor layer being electrically and permanently configured to said second low resistivity electrical state from said first high resistivity electrical state upon application of a threshold signal to said selected portions of said second semiconductor layer in contact with said metallic compound, said second semiconductor layer disposed in and between said apertures defined in said insulating layer; and

a plurality of conductive bit lines disposed on said second semiconductor layer and aligned at least with said metallic compound underlying said second semiconductor layer but without registration of any kind with respect to said underlying second semiconductor layer,

whereby cell densities in said memory are increased and having a decreased bit line and word line pitch without any increase in fabrication and alignment tolerances by which said memory is constructed.

10. An electrical programmable read-only memory comprising:

a semiconductor substrate;

a plurality of conductive word lines disposed on said substrate;

a first semiconductor layer composed of semiconductor material having a polycrystalline grain structure disposed on said plurality of word lines and on said substrate;

an insulating layer disposed upon said first semiconductor layer, said insulating layer having a plurality of apertures defined therethrough exposing portions of said first semiconductor layer, each of said apertures defined in said insulating layer being approximately aligned with one of said word lines disposed beneath said apertures and said first semiconductor layer;

a metallic compound in contact with said first semiconductor layer forming a plurality of Schottky diodes therewith, said metallic compound being disposed in the form of a two lateral dimensional layer within each of said apertures in said insulating layer, a Schottky diode being formed in each of said plurality of apertures;

a second semiconductor layer disposed at least within said apertures in said insulating layer in electrical contact with said metallic compound, said second semiconductor layer composed of semiconductor material having a first high resistivity and second low resistivity electrical state, selected portions of said second semiconductor material being electrically and permanently configured to said second low resistivity electrical state from said first high resistivity electrical state upon application of a threshold signal to said selected portions of said second semiconductor material in contact with said metallic compound, said second semiconductor layer disposed in and between said apertures defined in said insulating layer; and

a plurality of conductive bit lines disposed on said second semiconductor layer and aligned at least with said metallic compound underlying said second semiconductor layer but without registration of any kind with respect to said underlying second semiconductor layer, thereby avoiding limitations on the closeness of spacing of said conductive bit lines to each other on said insulating layer which limitations would have otherwise been encountered if said second semiconductor layer were selectively disposed on said insulating layer;

whereby cell densities in said memory are increased and having a decreased bit line and word line pitch without any increase in fabrication and alignment tolerances by which said memory is constructed.