Serial accessed semiconductor memory with reconfigurable shift registers

• US 4,796,231 A
• Filed: 06/25/1987
• Issued: 01/03/1989
• Est. Priority Date: 01/22/1985
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pinkham, Raymond
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/066,792
• Time in Patent Office: 558 Days
• Field of Search: 365/182, 365/189, 365/191, 365/193, 365/203, 365/215, 365/219, 365/220, 365/221, 365/233, 365/235, 340/700, 340/768
• US Class Current: 365/189.16
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory is comprised of four arrays (10), (12), (14) and (16) that have the memory elements therein arranged in accordance with pixel positions on a display. The memory arrays have associated shift registers (34), (36), (38) and (40) which have data loaded in parallel and output in a serial format to the display. Each of the shift registers can be connected in a circulating fashion or a shift register of adjacent arrays can be cascaded. Switches (56), (58), (60) and (62) are provided for configuring the shift registers for either circulation or cascading of data. In the circulating mode, the input and output of the shift registers is multiplexed on one pin whereas in the cascaded configuration, one array receives a dedicated serial input and the other array in the cascaded pair outputs the serial output on a dedicated pin.

Claims

1. A memory device, comprising:

a first plurality of addressable read/write memory cells, said memory cells arranged in rows and columns;

a second plurality of addressable read/write memory cells, said memory cells arranged in rows and columns;

a first register comprised of a third plurality of memory cells, each of said memory cells in said first register associated with one of said columns of said first plurality of memory cells, and each of said memory cells

a first serial output means for presenting the contents of a memory cell in said first register;

a second register comprised of a fourth plurality of memory cells, each of said memory cells in said second register associated with one of said columns of said second plurality of memory cells;

a second serial output means for presenting the contents of a memory cell in said second register;

row decode means, responsive to a row address signal, for selecting a row of memory cells in said first plurality of memory cells, and a row of memory cells in said second plurality of memory cells, said selected rows corresponding to said row address signal;

column decode means, responsive to a column address signal, for selecting a column of memory cells in said first plurality of memory cells, and a column of memory cells in said second plurality of memory cells, said selected columns corresponding to said column address;

input means for writing data to said memory cells at the intersection of said rows and columns selected by said row decode means and said column decode means;

output means for presenting the data stored by said memory cells at the intersection of said rows and columns selected by said row decode means and said column decode means;

means, responsive to a transfer signal, for transferring the contents of memory cells in said selected row of said first plurality of memory cells to said first register, and for transferring the contents of memory cells in said selected row of said second plurality of memory cells to said second register;

serial clock means, responsive to a serial clock signal, for shifting to said first serial output means the contents of another memory cell in said first register, and for shifting to said second serial output means the contents of another memory cell in said second register, so that, responsive to a series of said serial clock signals, the contents of a series of memory cells are presented by said first serial output means and said second serial output means; and

switch means having a first position and a second position for, in said first position, connecting said first serial output means to said second register so that, after the contents of a series of memory cells in said second register have been presented by said second serial output means, the contents of a series of memory cells in said first register are presented by said second serial output means, and for, in said second position, disconnecting said first serial output means from said second register.

2. The memory device of claim 1, wherein said switch means is set during the manufacture of the device to either said first position or said second position.

3. The memory device of claim 1, wherein said memory cells in said first register are arranged in a series from a first memory cell to a last memory cell therein;

wherein said memory cells in said second register are arranged in a series from a first memory cell to a last memory cell therein;

and further comprising;

a first coupling means for coupling to said first serial output means the contents of said first memory cell of said first register responsive to said serial clock signal occurring after said serial output means is presenting the contents of said last memory cell in said first register, said first coupling means operative when said switch means is in its second position; and

a second coupling means for coupling to said second serial output means the contents of said first memory cell of said second register responsive to said serial clock signal occurring after said serial output means is presenting the contents of said last memory cell in said second register, said coupling means operative when said switch means is in its second position.

4. The memory device of claim 3, wherein said switch means is set during the manufacture of the memory device to either said first position or said second position.

5. The memory device of claim 3, further comprising:

means for selecting the memory cell in said first register to be connected to said first serial output means, and for selecting the memory cell in said second register to be connected to said second serial output means;

wherein said selecting means is responsive to said column decode means.

6. The memory device of claim 5, wherein said first coupling means is for coupling to said first serial output means the contents of said selected memory cell of said first register responsive to said serial clock signal occurring after said serial output means presents the contents of said last memory cell in said first register;

and wherein said second coupling means is for coupling to said second serial output means the contents of said selected memory cell of said second register responsive to said serial clock signal occurring after said serial output means presents the contents of said last memory cell in said second register.

7. The memory device of claim 6, wherein said switch means is set during the manufacture of the memory device to either said first position or said second position.

8. The memory device of claim 1, further comprising:

a first serial input means for writing input data into a memory cell in said first register; and

a second serial input means for writing input data into a memory cell in said second register;

wherein said serial clock means is also for shifting the data written by said first serial input means to another memory cell in said first register and for shifting the data written by said second serial input means to another memory cell in said second register, responsive to said serial clock signal, so that, responsive to a series of said serial clock signals, data may be written into a series of memory cells in said first register and said second register.

9. The memory device of claim 8, wherein said switch means, in its first position, connects said first serial output means to said second serial input means.

10. The memory device of claim 9, wherein said memory cells in said first register are connected in a series from a first memory cell to a last memory cell therein;

wherein said memory cells in said second register are connected in a series from a first memory cell to a last memory cell therein;

wherein said first memory cell in said first register is connected to said first serial output means, and said last memory cell in said first register is connected to said first serial input means;

wherein said first memory cell in said second register is connected to said second serial output means, and said memory cell in said second register is connected to said second serial input means;

and wherein said serial clock means, responsive to said serial clock signal, shifts the contents of each memory cell in said first register and said second register into the next memory cell connected in series thereto.

11. The memory device of claim 10, further comprising:

a first coupling means for coupling said first serial output means to said first serial input means, said first coupling means operative when said switch means is in its second position; and

a second coupling means for coupling said second serial output means to said second serial input means, said coupling means operative when said switch means is in its second position.

12. The memory device of claim 11, wherein said switch means is set during the manufacture of the memory device to either said first position or said second position.

13. The memory device of claim 9, further comprising:

means for selecting the memory cell in said first register to be connected to said first serial output means, and for selecting the memory cell in said second register to be connected to said second serial output means;

wherein said selecting means is responsive to said column decode means.

14. The memory device of claim 13, wherein said memory cells in said first register are connected in a series from a first memory cell to a last memory cell therein;

wherein said memory cells in said second register are connected in a series from a first memory cell to a last memory cell therein;

wherein said last memory cell in said first register is connected to said first serial input means;

wherein said last memory cell in said second register is connected to said second serial input means;

and further comprising;

a first coupling means for coupling said first serial output means to said first serial input means, said first coupling means operative when said switch means is in its second position; and

a second coupling means for coupling said second serial output means to said second serial input means, said second coupling means operative when said switch means is in its second position.

15. The memory device of claim 14, wherein said switch means is set during the manufacture of the memory device to either said first position or said second position.