Write protect mechanism for non-volatile memory
First Claim
1. In a system comprising a PROM, a write protect register, clock means for providing a clock signal and write protect means for allowing writes to the PROM if and only if the write protect register contains predetermined data, a write protect control apparatus comprising:
- timer means responsive to the clock signal and to an external event to generate a timeout signal a predetermined number of cycles of the clock signal after the occurrence of the external event; and
register protect means responsive to the external event and to the timeout signal for allowing the writing of the predetermined data into the write protect register only in the period between the occurrence of the external event and the generation of the timeout signal.
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Accused Products
Abstract
A write protect mechanism for a programmable read-only memory prevents writes to the PROM unless a protect register contains predetermined information. The protect register is itself a write protected control register. The predetermined information cannot be written into the protect register except during a short, predetermined period after the occurrence of an event such as a reset. The protect register may be written to with information other than the predetermined information at any time. The preferred embodiment comprises a single-chip microcomputer with on-board electrically-erasable programmable read-only memory which is write protected in several, separate blocks.
84 Citations
17 Claims
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1. In a system comprising a PROM, a write protect register, clock means for providing a clock signal and write protect means for allowing writes to the PROM if and only if the write protect register contains predetermined data, a write protect control apparatus comprising:
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timer means responsive to the clock signal and to an external event to generate a timeout signal a predetermined number of cycles of the clock signal after the occurrence of the external event; and register protect means responsive to the external event and to the timeout signal for allowing the writing of the predetermined data into the write protect register only in the period between the occurrence of the external event and the generation of the timeout signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing system comprising:
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CPU means for executing instructions; reset means for resetting the system in response to an external event; clock means for generating a clock signal and a timeout signal, said time-out signal changes from a first state to a second state a predetermined time after the system is reset by said reset means; and PROM means for storing data, said PROM means being readable and writable by said CPU means under control of said instructions;
the data processing system being characterized by a write protect apparatus comprising;protect register means for storing information; write protect means for preventing said CPU means from writing to said PROM means, said write protect means being responsive to predetermined information stored in said protect register means to allow said CPU means to write to said PROM means; and means responsive to said time-out signal to allow said CPU means to store said predetermined information in said protect register means only if said time-out signal is in said first state. - View Dependent Claims (9, 10, 11, 12)
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13. In a system comprising a PROM, a write protect register, clock means for providing a clock signal and write protect means for allowing writes to the PROM if and only if the write protect register contains predetermined data, a method of protecting the PROM from inadvertent writes comprising the steps of:
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responding to an external event and to the clock signal by generating a timeout signal a predetermined number of cycles of the clock signal after the occurrence of the external event; and allowing the predetermined data to be written into the write protect register only during the period between the occurrence of the external event and the generation of the timeout signal. - View Dependent Claims (14, 15, 16, 17)
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Specification