Encryption printed circuit board
First Claim
1. An encryption/decryption apparatus for a host computer having expansion slots for an expander board comprising:
- an expander board for connection to a host computer'"'"'s expansion slot, said expander board including;
an address storage means, a control read/write means, and a data storage means for operative connection to a host computer, the address means for storing addresses for a block of data received from the host computer for ciphering and the read/write control means for receiving ciphering operational commands from the host computer including memory read, I/O read, I/O write, and enable control signals;
an auto-start means connected to the address storage means, control read/write means, and data storage means for coordinating the data addresses of the host computer with addresses for the expander board;
a register selector means connected to the auto-start memory means and to the control read/write means for outputting register selector signals;
a register means including a data input register connected to the control read/write means and data storage means and responsive to an I/O read enabling signal for storing the host computer'"'"'s data for ciphering, a read/write command status register connected to the control read/write means and responsive to an I/O write signal for storing the host computer'"'"'s command status signals, and a data output register connected to a microprocessor'"'"'s enable terminal and data storage means and responsive to an enable signal for reveiving ciphered data;
a cipher processor connected to the register means for receiving data for encryption or decryption selectively;
a microprocessor connected to the register means and to the cipher processor, the micropressor including an instruction means, and an instruction execution means for cycling through an I/O port read bus cycle, a memory-read bus cycle;
a data storage means connected to the cipher processor and to the microprocessor for storing the ciphered data output of the cipher processor; and
a key card interface means connected to the microprocessor, the key card interface means for connection to a key card reader for obtaining key information for the cipher processor;
whereby the microprocessor upon command of the host processor fetches key information from the key card interface means for user authentication and cipher processor code selection and responsive to an authentication signal cycling through an I/O port read bus cycle each time an IN instruction is executed, a memory-read bus cycle for fetching instructions and data for ciphering by the cipher processor, and I/O port write bus cycle each time an OUT instruction is executed for writing data to a specific I/O port address in the I/O address space of the microprocessor storage means, and a memory-write bus cycle each time an instruction is executed to write data to a valid memory location.
4 Assignments
0 Petitions
Accused Products
Abstract
An encryption printed circuit board (PCB) for use as an add on board to a host computer includes address registers, read/write controller, and data information transceiver adapted for connection to the host computer. The addresses registers are connected to a memory decode, auto-start PROM, I/O decoder and register select. The memory decoder is connected to the auto-start PROM and the I/O decoder is connected to the register select. A bus logic circuit is connected to the read/write controller, and outputs read/write signals to the data information transceiver and register select. The data information transceiver is connected to the auto-start PROM and to a plurality of data registers for receiving instructions from the auto-start PROM and inputting or receiving information from the data registers pursuant to instruction of the auto-start PROM program, and selection of the appropriate registers by the register select. A cipher processor, microprocessor, low address latch and memory, program, and buffer are connected to the data registers. The microprocessor is connected to a card reader through a card reader interface, and to an upper address decoder and the memory, program, buffer. Upon receipt of a load key instruction from the PC the microprocessor loads the key and a block of information from the input register into the cipher processor for either encryption or decryption and the processed block of information into the information output register for output to the PC upon receipt of a write instruction.
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Citations
9 Claims
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1. An encryption/decryption apparatus for a host computer having expansion slots for an expander board comprising:
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an expander board for connection to a host computer'"'"'s expansion slot, said expander board including; an address storage means, a control read/write means, and a data storage means for operative connection to a host computer, the address means for storing addresses for a block of data received from the host computer for ciphering and the read/write control means for receiving ciphering operational commands from the host computer including memory read, I/O read, I/O write, and enable control signals; an auto-start means connected to the address storage means, control read/write means, and data storage means for coordinating the data addresses of the host computer with addresses for the expander board; a register selector means connected to the auto-start memory means and to the control read/write means for outputting register selector signals; a register means including a data input register connected to the control read/write means and data storage means and responsive to an I/O read enabling signal for storing the host computer'"'"'s data for ciphering, a read/write command status register connected to the control read/write means and responsive to an I/O write signal for storing the host computer'"'"'s command status signals, and a data output register connected to a microprocessor'"'"'s enable terminal and data storage means and responsive to an enable signal for reveiving ciphered data;
a cipher processor connected to the register means for receiving data for encryption or decryption selectively;a microprocessor connected to the register means and to the cipher processor, the micropressor including an instruction means, and an instruction execution means for cycling through an I/O port read bus cycle, a memory-read bus cycle; a data storage means connected to the cipher processor and to the microprocessor for storing the ciphered data output of the cipher processor; and a key card interface means connected to the microprocessor, the key card interface means for connection to a key card reader for obtaining key information for the cipher processor; whereby the microprocessor upon command of the host processor fetches key information from the key card interface means for user authentication and cipher processor code selection and responsive to an authentication signal cycling through an I/O port read bus cycle each time an IN instruction is executed, a memory-read bus cycle for fetching instructions and data for ciphering by the cipher processor, and I/O port write bus cycle each time an OUT instruction is executed for writing data to a specific I/O port address in the I/O address space of the microprocessor storage means, and a memory-write bus cycle each time an instruction is executed to write data to a valid memory location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification