Encryption printed circuit board

• US 4,797,928 A
• Filed: 01/07/1987
• Issued: 01/10/1989
• Est. Priority Date: 01/07/1987
• Status: Expired due to Term

• Current Assignee: MIU Industries Limited 1600-609 Granville Street
• Original Assignee: MIU Automation Corporation
• Inventors: Dykes, John
• Primary Examiner(s): Buczinski, Stephen C.
• Application Number:
  US07/001,206
• Time in Patent Office: 734 Days
• Field of Search: 380/21, 380/23, 380/25, 380/29, 380/44, 380/49, 380/4
• US Class Current: 713/192
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

Abstract

An encryption printed circuit board (PCB) for use as an add on board to a host computer includes address registers, read/write controller, and data information transceiver adapted for connection to the host computer. The addresses registers are connected to a memory decode, auto-start PROM, I/O decoder and register select. The memory decoder is connected to the auto-start PROM and the I/O decoder is connected to the register select. A bus logic circuit is connected to the read/write controller, and outputs read/write signals to the data information transceiver and register select. The data information transceiver is connected to the auto-start PROM and to a plurality of data registers for receiving instructions from the auto-start PROM and inputting or receiving information from the data registers pursuant to instruction of the auto-start PROM program, and selection of the appropriate registers by the register select. A cipher processor, microprocessor, low address latch and memory, program, and buffer are connected to the data registers. The microprocessor is connected to a card reader through a card reader interface, and to an upper address decoder and the memory, program, buffer. Upon receipt of a load key instruction from the PC the microprocessor loads the key and a block of information from the input register into the cipher processor for either encryption or decryption and the processed block of information into the information output register for output to the PC upon receipt of a write instruction.

Claims

1. An encryption/decryption apparatus for a host computer having expansion slots for an expander board comprising:

an expander board for connection to a host computer'"'"'s expansion slot, said expander board including;

an address storage means, a control read/write means, and a data storage means for operative connection to a host computer, the address means for storing addresses for a block of data received from the host computer for ciphering and the read/write control means for receiving ciphering operational commands from the host computer including memory read, I/O read, I/O write, and enable control signals;

an auto-start means connected to the address storage means, control read/write means, and data storage means for coordinating the data addresses of the host computer with addresses for the expander board;

a register selector means connected to the auto-start memory means and to the control read/write means for outputting register selector signals;

a register means including a data input register connected to the control read/write means and data storage means and responsive to an I/O read enabling signal for storing the host computer'"'"'s data for ciphering, a read/write command status register connected to the control read/write means and responsive to an I/O write signal for storing the host computer'"'"'s command status signals, and a data output register connected to a microprocessor'"'"'s enable terminal and data storage means and responsive to an enable signal for reveiving ciphered data;

a cipher processor connected to the register means for receiving data for encryption or decryption selectively;

a microprocessor connected to the register means and to the cipher processor, the micropressor including an instruction means, and an instruction execution means for cycling through an I/O port read bus cycle, a memory-read bus cycle;

a data storage means connected to the cipher processor and to the microprocessor for storing the ciphered data output of the cipher processor; and

a key card interface means connected to the microprocessor, the key card interface means for connection to a key card reader for obtaining key information for the cipher processor;

whereby the microprocessor upon command of the host processor fetches key information from the key card interface means for user authentication and cipher processor code selection and responsive to an authentication signal cycling through an I/O port read bus cycle each time an IN instruction is executed, a memory-read bus cycle for fetching instructions and data for ciphering by the cipher processor, and I/O port write bus cycle each time an OUT instruction is executed for writing data to a specific I/O port address in the I/O address space of the microprocessor storage means, and a memory-write bus cycle each time an instruction is executed to write data to a valid memory location.

2. An encryption/decryption apparatus according to claim 1 wherein the control read/write is a logic circuit means for producing read/write signals for the data storage means and read/write terminals of the microprocessor.

3. An encryption/decryption apparatus according to claim 1 wherein the address storage means and data storage means including, respectively, a plurality of address buffers for storing the host computer'"'"'s addresses for the host computer data to be ciphered and returned, and a data buffer for storing the data to be ciphered and the ciphered data for return to the host computer.

4. An encyption/decryption apparatus according to claim 1 wherein the key card interface means includes an EEPROM key card reader.

5. An encryption/decryption apparatus according to claim 4 wherein the key card reader further includes secondary key information for the cipher processor for preventing the linkage of files together in storage.

6. An encryption/decryption apparatus according to claim 1 wherein the I/O port read bus cycle of the microprocessor instruction means and instruction execution means includes means responsive to an IN instruction for issuing an instruction to fetch data from I/O port addresses in one of the plurality of address registers, means for determining whether the addresss bus bits contain a valid I/O port address, means for activating the I/O read bus control for indicating both that the bus cycle is an I/O port read cycle and that the addressed port should respond by driving the data bus with its contents, means connected to the host computer for sampling the data on the data bus, and means for deactivating the I/O read bus signal.

7. An encryption/decryption apparatus according to claim 1 wherein the memory-read bus cycle of the microprocessor instruction means includes means for determining that the address bus contains a valid memory address, means for activating the memory-read bus signal for indicating to the devices attached to the bus that the cycle is a memory-read cycle, said devices responsive to the memory-read cycle indicating signal for driving the data bus with its contents through the cipher processor selectively for encryption and decryption, and means enabling the microprocessor to capture the data from the data bus.

8. An encryption/decryption apparatus according to claim 1 wherein the I/O port write bus cycle of the microprocessor instruction means includes means responsive to an OUT instruction to write data to a specific I/O port address in the I/O address space of the microprocessor, means for indicating that the addresss bus contains a valid port address, means for activating the bus control signal I/O write to indicate that the bus cycle is an I/O port write cycle and means directing the selected port address to take data from the data bus, means instructing the microprocessor to drive the data bus with the data for the port address, and means for deactivation the I/O write bus control signal.

9. An encryption/decryption apparatus according to claim 1 wherein the memory-write bus cycle of the microprocessor instruction means includes means responsive to an instruction to write data to a memory location for activating the microprocessor and its bus buffers for driving an address onto the host computer'"'"'s system bus, means for indicating the address of the memory location that should accept the data, means enabling the microprocessor to drive the data bus with the data that is to be written in the selected memory location, means indicating that the address bus contains a valid memory address, means for activating the memory write bus signal, and means for driving the host processor'"'"'s system bus with the ciphered data for storage in the selected memory location and means for deactivating the memory-write signal.