Integrated circuit comprising a latch-up protection circuit in complementary MOS-circuitry technology
First Claim
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1. An integrated circuit, comprising:
- a doped semiconductor substrate;
complementary MOS-circuitry in the substrate;
a substrate bias voltage terminal in the doped semiconductor substrate connected to an output of a substrate bias voltage generator;
a capacitor having first and second capacitor surfaces, the first capacitor surface being integrated in the doped semiconductor substrate, and the second capacitor surface being connected via an electronic protection circuit means to a capacitor bias voltage generator; and
said electronic protection circuit means interconnecting the second capacitor surface and the capacitor bias voltage generator following a delay time Δ
T when the integrated circuit is switched on.
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Abstract
An integrated circuit has a storage cell and complementary MOS-circuit technology. A substrate bias voltage generator connects a semiconductor substrate having a well region inserted therein to a substrate bias voltage. In order to avoid latch-up effects, an electronic protection circuit connects a current path, for charging a capacitor of the storage cell, only after a delay time ΔT following a switch-on of the integrated circuit.
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Citations
15 Claims
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1. An integrated circuit, comprising:
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a doped semiconductor substrate; complementary MOS-circuitry in the substrate; a substrate bias voltage terminal in the doped semiconductor substrate connected to an output of a substrate bias voltage generator; a capacitor having first and second capacitor surfaces, the first capacitor surface being integrated in the doped semiconductor substrate, and the second capacitor surface being connected via an electronic protection circuit means to a capacitor bias voltage generator; and said electronic protection circuit means interconnecting the second capacitor surface and the capacitor bias voltage generator following a delay time Δ
T when the integrated circuit is switched on. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An integrated circuit, comprising:
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a substrate having at least a first FET of first channel conductivity type and a complementary second FET of second conductivity type, and a well-like zone in the substrate containing one of said first and second FETs; a storage cell in the substrate formed of a third FET connected to a capacitor having first and second surfaces, the first surface being a doped region surrounded by the substrate and a second surface overlying the first surface; a substrate bias voltage terminal in the substrate; a substrate bias voltage generator connected at one side to a supply voltage and at the other side to said substrate bias voltage terminal; a bias voltage generator connected at one side to a supply voltage and at an opposite side through an electronic protection circuit to said second surface of the capacitor; and said electronic protection circuit having means for interconnecting the second capacitor surface and the capacitor bias voltage generator following a delay time Δ
T when the integrated circuit is activated.
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Specification