Display control apparatus

• US 4,799,000 A
• Filed: 09/30/1986
• Issued: 01/17/1989
• Est. Priority Date: 09/30/1986
• Status: Expired due to Fees

• Current Assignee: Magnavox Electronic Systems Company
• Original Assignee: Magnavox Government and Industrial Electronics Company
• Inventors: Close, Ernest F.
• Primary Examiner(s): Blum, Theodore M.
• Application Number:
  US06/913,768
• Time in Patent Office: 840 Days
• Field of Search: 315/371, 315/370, 315/382, 315/368, 315/367
• US Class Current: 315/371
• CPC Class Codes: H04N 3/2335 with calculating means
• CPC Class Codes: H04N 9/28 Arrangements for convergence or focusing

Abstract

Horizontal and vertical deflection windings in a deflection yoke coil assembly of a CRT (cathode ray tube) having stroke written or raster scan displays are driven by x and y analog deflection signals, respectively. Each of the x and y analog deflection signals are converted to x and y digital signals, respectively, sampled to provide x, y sample sets which are coupled to a digital x correction signal memory and a digital y correction signal memory, respectively. Geometric corrections are stored in the memories for each of a predetermined number of x, y signal set values which correspond, respectively, to a number of point locations over the CRT screen. The x and y corrections that are addressed from the memories are supplied to MDACs (multiplying digital to analog converters) and then to analog delay line filters which supply the x, y analog correction signals for summing with the x, y analog deflection signals, respectively. The x and y digital signals are also coupled to separate astigmatism, dynamic focus, shading and convergence memories which are coupled to DACs (digital to analog converters) and then to respective CRT controls or associated circuitry.

Claims

1. Display control apparatus for use with a CRT having an electron gun beam and an electron beam activated screen, x and y analog signal sources for providing, respectively, horizontal and vertical deflection of the electron beam, and having at least one CRT display control member, that improvement comprising:

memory means for storing and addressing digital data;

first analog to digital converter means coupled between the x analog signal source and said memory means for converting the x analog deflection signal to a corresponding x digital deflection signal;

second analog to digital converter means coupled between the y analog signal source and said memory means for converting the y analog deflection signal to a corresponding y digital deflection signal;

sampling means coupled to said first and said second analog to digital converter means for simultaneously sampling each of the x and y digital signals, whereby an x, y digital sample set is provided from said first and said second analog to digital converter means;

each of said sample sets corresponding to a respective predetermined point location on the screen;

said point locations being spaced one from another over a predetermined portion of the entire viewed area of said screen;

said memory means for storing digital data relating to at least one CRT display control member for each of said digital sample sets;

said memory means for using said x, y digital sample sets to address said digital data;

digital to analog converter means coupled to said memory means for converting said addressed digital data to corresponding analog signals;

coupling means for coupling said digital to analog converter means to the display control member;

whereby each of said digital sample sets provides an address for respective digital data in said memory means to provide real time geometrically corrected analog signals to the display control member.

2. The apparatus of claim 1 wherein said CRT display control member comprises the CRT horizontal and vertical deflection windings;

said memory means comprising first memory means for storing digital geometric corrections to the x deflection signal for each of said x, y digital sample sets;

second memory means for storing digital geometric corrections to the y deflection signal for each of said x, y digital sample sets;

said digital to analog converter means comprising first and second digital to analog converter means coupled to said first and second memory means, respectively, for converting the x and y digital correction signals for each of said predetermined number of x, y signal set values to x and y analog correction signals, respectively;

each of said first and second digital to analog converter means comprising a multiplying digital to analog converter means having a reference port;

said reference ports of said first and second digital to analog converter means being coupled to said x and y signal sources respectively to provide a sliding reference to said first and second digital to analog converter means and to smooth the analog output from each of said first and second digital to analog converter means.

3. The apparatus of claim 1 including x and y analog signal sources and at least one CRT display control member;

said x and y analog signal sources being coupled to said at least one display control member;

delay line means being coupled between each of said x and y signal sources and said control member for delaying the analog signals from said x and y signal sources by a time delay substantially equal to the time required for the conversion between digital and analog signals and the digital signal processing.

4. The apparatus of claim 3 wherein said CRT display control member comprises a CRT horizontal and vertical deflection winding.

5. The apparatus of claim 1 wherein said sampling means comprises clock means coupled to said analog to digital converter means for providing a signal at a clock frequency to said analog to digital converter means to provide said x, y digital sample sets at said clock frequency from said analog to digital converter means.

6. The apparatus of claim 5 including latch means coupled between said memory means and said digital to analog converter means for providing a temporary memory storage for the most recent output from said memory means;

said clock means being coupled to said latch means to couple signals between said memory means and said digital to analog converter means at said clock frequency;

whereby transient signals and noise generated between the periodic intervals between clock signals are not coupled to said digital to analog converter means.

7. The apparatus of claim 2 including filter means coupled between each of said multiplying digital to analog converters and said horizontal and vertical deflection windings respectively for further smoothing the analog signals from said multiplying digital to analog converters;

said filter means comprising an operational amplifier having inverting and noninverting inputs and an output, an input port and a plurality of delay line ports;

the signal at each successive delay line port being delayed more than the signal at the next previous delay line port for a given signal at said input port;

said delay line ports being coupled to said inverting input;

a capacitor and resistor being connected in parallel and coupled between said operational amplifier inverting input and output.

8. The apparatus of claim 1 wherein said CRT display control member includes at least one of an electron beam deflection member, display dynamic focus control member, display shading control member, and electron beam convergence member.

9. The apparatus of claim 1 wherein said CRT display control member includes an electron beam deflection member, display dynamic focus control member, display shading control member, and electron beam convergence member.

10. The apparatus of claim 1 wherein said CRT display control member comprises a dynamic focus control member;

means for receiving instantaneous writing rates and an operator entered brightness level and effectively obtaining the product of said brightness level and said writing rates;

said memory means comprising means for storing focus correction digital data relating to said dynamic focus control member for each of said products;

said memory means for using each of said products to address said focus correction digital data corresponding to said each of said products.

11. The apparatus of claim 1 including decode logic means coupled to said first and second analog to digital converter means for receiving said x, y sample sets and for providing signals indicating the maximum desired x and y deflection signals for scaling and centering of the x, y deflection signals so that said first and second analog to digital converter means operate over their respective full ranges.

12. The apparatus of claim 11 wherein said decode logic means is for providing a signal indicating the x, y deflection signals have exceeded said maximum deflection for said x and y deflection signals and for inhibiting CRT display during the period said maximum deflection signal is being exceeded.

13. The apparatus of claim 1 including means for providing an adjustment to obtain orthogonality between said x and y analog deflection signals.

14. The apparatus of claim 1 including means for providing buffering of the analog x and y deflection signal and for buffering signals from each of said digital to analog converter means.

15. Display control apparatus for use with a cathode ray tube having an electron gun beam and an electron beam activated screen and having horizontal and vertical deflection windings coupled to x and y analog deflection signal sources, respectively, that improvement comprising:

first memory means for storing digital geometric corrections to the x deflection signal for each of a predetermined number of x, y signal sets, each x, y signal set corresponding to a respective predetermined geometrically correct point location on the screen;

second memory means for storing digital geometric corrections to the y deflection signal for each of said predetermined number of x, y signal sets;

first analog to digital converter means coupled between the x analog signal source and each of said first and second memory means and for converting the x analog deflection signal to an x digital deflection signal;

second analog to digital converter means coupled between the y analog signal source and each of said first and second memory means and for converting the y analog deflection signal to a y digital deflection signal, so that an x digital correction signal is called from said first memory means for each x, y signal set and a y digital correction signal is called from said second memory means for each x, y signal set;

first and second digital to analog converter means coupled to said first and second memory means, respectively, for converting the x and y digital correction signals for each of said predetermined number of x, y signal sets to x and y analog correction signals, respectively;

first summing means coupled to said first digital to analog converter means and to the x analog signal source for summing said x analog correction signal to the x analog signal to provide a corrected x analog deflection signal;

second summing means coupled to said second digital to analog converter means and to the y analog signal source for summing said y analog correction signal to the y analog signal to provide a corrected y analog deflection signal;

whereby the x and y analog deflection signals are real time geometrically corrected to provide x and y analog signals to the x and y deflection windings respectively so that the x and y deflection windings will precisely position the electron gun beam at said respective predetermined geometrically correct point locations on the screen.