Semiconductor testing device

• US 4,799,009 A
• Filed: 03/31/1983
• Issued: 01/17/1989
• Est. Priority Date: 10/25/1979
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: VLSI Technology Research Association (Koninklijke Philips N.V.)
• Inventors: Okada, Keisuke, Tada, Tetsuo
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US06/479,117
• Time in Patent Office: 2,119 Days
• Field of Search: 324/158 F, 324/158 P, 324/72.5
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A wafer testing device in which a plurality of wafers can be tested simultaneously significantly reducing the time required for testing each chip. A prober is provided which receives a wafer to be tested. A probe card is coupled to the prober having a window through which a plurality of semiconductor memory chips on the wafer are observable. A plurality of probes are coupled to the periphery of the window in such a manner that the probes can be brought into contact with bonding pads on the plurality of semiconductor memory chips. A tester is connected to the probes which is capable of simultaneously testing each of the plurality of chips.

Claims

1. A semi-conductor testing device comprising a prober adapted to receive a wafer to be tested, a probe card coupled to said prober, said probe card having a single rectangular window through which four identical semi-conductor chips on said wafer may be observed simultaneously, a first set of probes having free contact ends being mounted along two adjacent sides of said window with said free contact ends being disposed in a contact pattern adjacent one corner of said rectangular window and a second set of probes having free contact ends being mounted along the remaining two sides of said rectangular window with said free contact ends being disposed in an identical contact pattern adjacent a corner of said rectangular window diagonally opposite the first mentioned corner wherein said probes in each set are adapted to be connected to a common set of lead wires whereby two semi-conductor chips can be tested simultaneously.

2. A semi-conductor testing device as set forth in claim 1 wherein the free contact ends of each set of probes are disposed in a substantially rectangular pattern.