Display system having extended raster operation circuitry

• US 4,799,056 A
• Filed: 04/08/1987
• Issued: 01/17/1989
• Est. Priority Date: 04/11/1986
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Miyazaki, Yoshihiro, Iwami, Tomoyuki, Ohbuchi, Ryutaroh, Hattori, Etsuo
• Primary Examiner(s): Curtis, Marshall M.
• Assistant Examiner(s): FATAHI YAR, MAHMOUD
• Application Number:
  US07/035,955
• Time in Patent Office: 650 Days
• Field of Search: 340/701, 340/702, 340/703, 340/750, 340/747, 340/799, 364/521, 364/526
• US Class Current: 345/561
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A display system having a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, and a controller for controlling image data operations. The display system is provided with an extended raster operation circuitry comprising an intraplane operation unit and an interplane operation unit. Operation results of the circuitry are written back to the frame buffer. The respective operation units perform operations specified by the controller. The intraplane operation unit performs operations on image data in each of the memory planes, separately, while the interplane operation unit performs operations on image data in at least two memory planes selected by the controller. There are no restrictions as to the positional relation between the intraplane operation unit and the interplane operation unit.

Claims

1. A display system comprising:

a frame buffer for storing information representing one or more images, said information being organized into a plurality of memory planes;

a display device for visually displaying images stored in said frame buffer;

an extended raster operation circuit for performing logical operations on information in the frame buffer and for storing the results of the logical operations in the frame buffer; and

a controller for controlling the extended raster operation circuit;

characterized in that the extended raster operation circuit comprises;

an intraplane operation unit for performing intraplane logical operations specified by the controller on information in the frame buffer, each intraplane logical operation having at least one input operand and at least one output result, all operands and results of a given intraplane logical operation being in a single memory plane; and

an interplane operation unit for performing interplane logical operations specified by the controller on the results of the intraplane logical operations, each interplane logical operation having at least one input operand and at least one output result, the operands and results of a given interplane logical operation being in at least two memory planes.

2. A display system as claimed in claim 1, characterized in that the extended raster operation circuitry comprises:

a buffer register for retaining information read out of the frame buffer; and

a command circuit for receiving commands from the controller, said commands specifying logical operations to be performed by the extended raster operation circuitry and specifying the selection of memory planes.

3. A display system as claimed in claim 2, characterized in that:

the intraplane operation unit has an input connected to the buffer register; and

the results of the interplane logical operation are written back to the frame buffer.

4. A display system as claimed in claim 3, characterized in that the interplane operation unit comprises:

a plurality of logical operation circuits, one logical operation circuit for each memory plane, each logical operation circuit having first and second inputs and an output, the first input receiving the intraplane logical operation results from any selected memory plane, the output providing results for the associated memory plane in the frame buffer; and

a plurality of delay means, one delay means for each logical operation circuit, each delay means having an input and an output, the input of each delay means being connected to the output of the associated logical operation circuit, the output of each delay means being connected to the input of the associated logical operation circuit.

5. A display system comprising:

a frame buffer for storing information representing one or more images, said information being organized into a plurality of memory planes;

a display device for visually displaying images stored in said frame buffer;

an extended raster operation circuit for performing logical operations on information in the frame buffer and for storing the results of the logical operations in the frame buffer; and

a controller for controlling the extended raster operation circuit;

characterized in that the extended raster operation circuit comprises;

an interplane operation unit for performing logical operations specified by the controller on the information in the frame buffer, each interplane logical operation having at least one input operand and at least one output result, the operands and results of a given interplane logical operation being in at least two memory planes; and

an intraplane operation unit for performing logical operations specified by the controller on the results of the interplane operation unit, each intraplane logical operation having at least one input operand and at least one output result, all operands and results of a given intraplane logical operation being in a single memory plane.

6. A display system as claimed in claim 5, characterized in that the extended raster operation circuitry comprises:

a buffer register for retaining information read out of the frame buffer; and

a command circuit for receiving commands from the controller, said commands specifying logical operations to be performed by the extended raster operation circuitry and specifying the selection of memory planes.

7. A display system as claimed in claim 6, characterized in that:

the interplane operation unit has an input connected to the buffer register; and

the results of the intraplane logical operation are written back to the frame buffer.

8. A display system as claimed in claim 7, characterized in that the interplane operation unit comprises:

a plurality of logical operation circuits, one logical operation circuit for each memory plane, each logical operation circuit having first and second inputs and an output, the first input receiving information from the frame buffer from any selected memory plane, the output providing results for the intraplane operation unit; and

a plurality of delay means, one delay means for each logical operation circuit, each delay means having an input and an output, the input of each delay means being connected to the output of the associated logical operation circuit, the output of each delay means being connected to the input of the associated logical operation circuit.