System for displaying graphic information on video screen employing video display processor

• US 4,799,146 A
• Filed: 06/19/1985
• Issued: 01/17/1989
• Est. Priority Date: 06/29/1984
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): CLARK, DAVID
• Application Number:
  US06/746,422
• Time in Patent Office: 1,308 Days
• Field of Search: 340/723, 340/725, 340/747, 340/703, 340/750, 364/200 MS File, 364/900 MS File, 364/521, 364/518, 364/200
• US Class Current: 710/260
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A system which interprets the contents of address and data fields provided by a central processing unit 1 which controls the display. The address fields are selectively interpreted to obtain a direct access by the central processing unit to a general system memory 5, or so as to constitute instructions for a video processor 2. In this latter case, the address controls an operation cycle of a first priority for controlling the processor or executes a series of operations with a lower priority, such lower priority operations allowing processor 2 to process image information without the intervention of the central unit. The invention finds application in such areas as teletext systems and video games.

Claims

1. A system for displaying graphic information on a video screen, comprising:

memory means having a plurality of addressable memory locations in which said graphic information is to be stored;

a central processing unit for controlling the information to be displayed;

video display processor means for producing said graphic information and for storing said graphic information in said memory means;

communication bus means interconnecting said memory means, said central processing unit, and said video display processor means, said central processing unit presenting information on said communication bus means as time-multiplexed address and data fields, said address field defining an address space having first and second value ranges, said first value range of the address space defined by said address field corresponding to locations in said memory means addressable by said central processing unit, said second value range of the address space defined by said address field corresponding to a set of instructions for the video display processor means;

said video display processor means being connected to said memory means for accessing and modifying the contents of locations in said memory means containing said graphic information;

control circuit means connected to said central processing unit, said video display processor means and said memory means for controlling access to said memory means by said video display processor means and said central processing unit;

interpretation means connected to said communication bus means, said control circuit means and said video display processor means for decoding the address fields presented by said central processing unit on said communication bus means;

said control circuit means being responsive to receiving a decoded address value in said first value range of said address space defined by said address field for enabling access between said central processing unit and said memory means, and being responsive to receiving a decoded address value in said second value range of said address space defined by said address field for controlling said video display processor means to execute an instruction corresponding to the value of said address field;

an address value providing access to said memory means from said central processing unit having a predetermined priority of operation over an address value defining an instruction to be executed by said video display processor means; and

said interpretation means interrupting the operation of one of said instructions being executed by said video display processor means in response to the reception of an address value in said first value range of said address space defined by said address field corresponding to an operation of higher priority.

2. A system as set forth in claim 1, wherein said second value range of the address space defined by said address field includes first and second value range sectors corresponding to foreground instructions and background instructions respectively for said video display processor means;

a foreground instruction relating to the placement of consecutive data by said central processing unit into said video display processor means, a background instruction relating to one of a series of memory cycles directed by said central processing unit to be executed by said video display processor means, and said foreground instructions having a higher priority of execution compared to said background instructions as determined by said control circuit means; and

said interpretation means interrupting the operation of one of said background instructions being executed by said video display processor means in response to the reception of an address value in said first value range sector of said second value range of the address space defined by said address field identifying a foreground instruction.

3. A system as set forth in claim 2, wherein said interpretation means comprises

a decoder having inputs connected to said central processing unit and a plurality of output lines, the state of said plurality of output lines being a function of the value of the address field applied to the inputs of said decoder by said central processing unit;

address register means connected between said central processing unit and said communication bus means for receiving a memory address of a storage location within said memory means from said central processing unit;

data register means connected between said central processing unit and said communication bus means for transferring the value of a data field from the central processing unit to said communication bus means;

foreground register means connected to selected ones of said plurality of output lines of said decoder; and

background register means connected to said data register means and responsive to a background instruction from said video display processor means for storing the contents of a data field;

said interpretation means enabling the execution of one or a series of background instructions following reception of a value of said address field in said second value range sector of said second value range; and

said decoder being responsive to a value of said address field having a higher priority than the background instructions of said second value range sector of said second value range of the address space to enable said address register means, said data register means, and said foreground register means for reading or writing as a function of the instruction corresponding to the value of the address field.

4. A system as set forth in claim 3, further including second memory means having addressable memory locations for storing microinstructions therein for controlling said video display processor means;

said foreground register means and said background register means being connected to said second memory means; and

said microinstructions stored in said second memory means being selectively addressable by said video display processor means based upon the values stored in said foreground register means and said background register means.

5. A system as set forth in claim 4, wherein said plurality of output lines of said decoder includes two output lines connected to said control circuit means to enable access to said memory means according to the value of said address field;

and

said control circuit means having a plurality of outputs indicating access priorities connected to the inputs of said second memory means to enable retrieval of the microinstruction selected by the contents of said foreground register means and said background register means