Resynthesized digital radio frequency memory

• US 4,799,189 A
• Filed: 07/26/1985
• Issued: 01/17/1989
• Est. Priority Date: 07/26/1985
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Grover, R. Kent
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Kulik, Paul
• Application Number:
  US06/759,216
• Time in Patent Office: 1,271 Days
• Field of Search: 364/577, 364/723, 364/515, 364/516, 364/517, 364/571, 364/900 MS File, 364/200 MS File, 364/484, 364/487, 364/723, 364/602, 364/200, 364/900, 342/77, 342/195, 342/199, 342/98, 342/99, 342/102, 342/103, 369/4, 369/59, 369/60, 369/61, 369/174, 371/23, 371/30, 371/31, 371/32, 371/40, 371/42, 375/104, 375/112, 375/106, 375/92, 375/4, 375/94, 375/95, 360/22, 360/24, 360/26, 360/32, 455/18, 455/20, 455/63, 340/347 CC
• US Class Current: 369/61
• CPC Class Codes: G11C 2207/16 Solid state audio
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

The present invention describes a resynthesized DRFM and method thereof. A conventional DRFM is utilized with the addition of a computer device. Once the digital pattern signals are stored they are utilized to generate a digital pattern which fills the interpulse period between the pair of signals. The interpulse digital pattern is then adjusted so that the digital pattern phases of the first and second signals match. In general the interpulse period digital pattern is not a uniform replication of the pulsed signal digital pattern because the adjustments have been made in order to accomplish pattern phase between the two pulses. These are then stored in memory until recalled.

Claims

1. A resynthesized digital radio frequency memory (DRFM) for accurately representing an RF input signal utilizing a short pulse sampling signal of insufficient width to represent the input signal frequency, said digital radio frequency memory comprising:

an analog-to-digital converter having an RF input, a clock input and an output;

memory means for storing a first digital pattern, a second digital pattern and an interpulse digital pattern, said memory means having a first input, a second input, a first output, a second output and a control line, said first input being coupled to said output of said analog-to-digital converter, said memory means operating to store said first, second and interpulse digital patterns contiguously from a starting address to stopping address;

a digital-to-analog converter having an input, a clock input and an RF output, said input being coupled to said first output of said memory means;

control means for controlling the starting and stopping addresses for said digital patterns stored in said memory means, said control means having a clock input and an output, said output being coupled to said control line of said memory means;

timing means for timing the resynthesized DRFM, said timing means having an output coupled to said clock input of said analog-to-digital converter, to said clock input of said digital-to-analog converter, and to said clock input of said control means, said timing means operating to produce a timing frequency signal for said sampling of said RF input at a fractional ratio; and

computer means for generating an interpulse digital pattern from said first digital pattern and finding and correcting errors resulting from said sampling at a fractional ratio of said RF input signal utilizing said timing frequency signal, said timing frequency signal and said RF input signal being non-multiples, said generating including comparing said interpulse digital pattern with said second digital pattern and altering said interpulse digital pattern so that said first digital pattern and said second digital patterns match bit-for-bit for correcting a phase relationship of said first and second digital patterns to accurately represent said RF input signal, said computer means having an input and an output, said input being coupled to said second output of said memory means and said output being coupled to said second input of said memory means.

2. The resynthesized DRFM of claim 1 wherein said memory means consists of a random access memory device having a first input, a second input, a first output, a second output, and a control line, said first input being coupled to said output of said analog-to-digital converter, said second input being coupled to said output of said computer means, said first output being coupled to said input of said digital-to-analog converter, said second output being coupled to said input of said computer means, and said control line being coupled to said output of said control means.

3. A method of providing a resynthesized digital radio frequency signal from a RF input signal, a resynthesized digital radio frequency memory (DRFM) for accurately representing said RF input signal by utilizing a short pulse sampling signal of insufficient width to represent the input signal frequency, said DRFM having an input and an output and including an analog-to-digital converter, memory means for storing a digital pattern set, said memory means operating to store said digital pattern sets contiguously from a starting address to a stopping address, a digital-to-analog converter, control means for controlling the starting and stopping addresses for said digital pattern sets in said memory means, timing means for timing the resynthesized DRFM for sampling said RF input signal at a fractional ratio rate which is not a multiple of said RF signal input, and computer means for determining an interpulse pattern set between at least two digital pattern sets, said method comprising the steps of:

receiving a first analog signal of said RF input signal having a frequency at an input of said analog-to-digital converter;

converting said first analog signal into a first digital pattern set by sampling said first analog signal at said fractional ratio rate;

storing said first digital pattern set in said memory means;

receiving an interpulse analog duration at said input of said analog-to-digital converter;

converting said interpulse analog duration into an interpulse digital duration by sampling said interpulse analog duration at said fractional ratio rate;

storing said interpulse digital duration in said memory means contiguously with said first digital pattern set;

receiving a second analog signal of said RF input signal at said input of said analog-to-digital converter;

converting said second analog signal into a second digital pattern set by sampling said second analog signal at said fractional ratio rate;

storing said second digital pattern set in said memory means contiguously with said interpulse digital duration;

transferring said first digital pattern set and interpulse digital duration to said computer means;

generating an interpulse digital pattern set;

transferring said second digital pattern set to said computer means;

comparing said generated interpulse digital pattern set to said second digital pattern set;

adjusting said interpulse digital pattern set so that said first digital pattern set compares bit-for-bit with said second digital pattern set to correct a phase relationship of said first and second digital pattern sets to accurately represent said RF pulse input utilizing a relatively short pulse width sampling signal;

storing said first, said adjusted interpulse, and said second digital pattern sets contiguously in said memory means;

transmitting said first, said adjusted interpulse, and said second digital pattern sets to said digital-to-analog converter;

converting said first, said adjusted interpulse, and said second digital pattern sets to analog signals;

transmitting said analog signals to said output of said resynthesized DRFM; and

repeating said previous steps of said method on subsequent RF input signals to create said continuous wave resynthesized digital radio frequency signal of approximately the frequency of said received RF input signals.

4. The method of claim 3 wherein said memory means consists of a random access memory device having a first input, a second input, a first output, a second output, and a control line, said first input being coupled to an output of said analog-to-digital converter, said second input being coupled to an output of said computer means, said first output being coupled to an input of said digital-to-analog converter, said second output being coupled to an input of said computer means, and said control line being coupled to an output of said control means.