Semiconductor random access nonvolatile memory device with restore and control circuits

• US 4,799,194 A
• Filed: 02/20/1987
• Issued: 01/17/1989
• Est. Priority Date: 02/27/1986
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Arakawa, Hideki
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Garcia, Alfonso
• Application Number:
  US07/016,729
• Time in Patent Office: 697 Days
• Field of Search: 365/154, 365/185, 365/156, 365/190, 365/189, 365/226, 365/228, 365/184
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

In a nonvolatile memory device which is integrated by combining SRAM cells and nonvolatile memory cells at a ratio of 1:1; a control circuit is provided which, at a recall time, selects all word lines and supplies a predetermined electric potential to bit lines, so that a recall is carried out simply and accurately.

Claims

1. A semiconductor nonvolatile memory device comprising:

a pair of bit lines;

a plurality of word lines;

decoder means, coupled to said plurality of word lines, for selecting one of said word lines;

first and second transfer gate transistors having gates connected to one of said word lines;

a plurality of memory cells, each of said memory cells including;

a static memory cell including a flip-flop having first and second terminals connected between said pair of bit lines by way of said first and second transfer gate transistors; and

a nonvolatile memory cell connected to said first and second terminals of said flip-flop; and

a control circuit, operatively connected to said word lines, one of said bit lines and said decoder means, for selecting all of said word lines, turning on said first and second transfer gate transistors in said memory cells when information stored in said nonvolatile memory cell is recalled to said static memory cell, and supplying a predetermined potential to said flip-flop through said bit lines, said first and second transfer gate transistors making said flip-flop a predetermined state.

2. A semiconductor nonvolatile memory device according to claim 1, wherein said flip-flop includes cross-coupled complementary type inverters said first transfer gate transistor connected between one of said bit lines and said first terminal, and said second transfer gate transistor connected between the other one of said bit lines and said second terminal, and

wherein said nonvolatile memory cell includes a nonvolatile memory transistor, and said semiconductor nonvolatile memory device further comprises:

a third transfer gate transistor connected between said nonvolatile memory transistor and one of said first and second terminals.

3. A semiconductor nonvolatile memory device according to claim 2, wherein said complementary type inverters include a load transistor connected to said third transfer gate transistor, and a relationship between said load transistor and said nonvolatile memory transistor is as shown by the following equation:

##EQU2## wherein W denotes a channel width and L denotes a channel length.

4. A semiconductor nonvolatile memory device according to claim 2, wherein said third transfer gate transistor is turned on after said static memory cell reaches the predetermined state.

5. A semiconductor nonvolatile memory device, comprising:

a pair of bit lines;

a plurality of word lines;

decoder means, coupled to said plurality of word lines, for selecting one of said word lines;

first and second transfer gate transistor having gates connected to one of said word lines;

a plurality of memory cells, each of said memory cells including;

a static memory cell including a flip-flop having first and second terminals connected between said pair of bit lines by way of said first and second transfer gate transistors; and

a nonvolatile memory cell connected to said flip-flop;

a control circuit, operatively connected to said word lines, said bit lines, and said decoder means, for selecting all of said word lines, turning on said first and second transfer gate transistors in said memory cells when information stored in said nonvolatile memory cell is recalled to said static memory cell, and supplying a predetermined potential to said flip-flop through said bit lines, said first and second transfer gate transistors making said flip-flop a predetermined state, said control circuit including a bit line level control circuit, connected to one of said bit lines, for supplying a predetermined potential to one of said bit lines in response to a first control signal;

a row decoder, connected to said word lines, for selecting one of said word lines;

an output gate circuit connected to said bit lines;

a column decoder, connected to said output gate circuit, for controlling said output gate circuit;

a first gate circuit, connected between said row decoder and said word lines, for inhibiting an output of said row decoder in response to a second control signal and outputting a selection signal to all of said word lines in response to a third control signal;

a second gate circuit, connected between said column decoder and said output gate circuit, for inhibiting transfer of an output of said column decoder and turning said output gate circuit off in response to the second control signal; and

a timing generator circuit, connected to said first and second gate circuits and said bit line level control circuit, for generating the first, second and third control signals.

6. A semiconductor nonvolatile memory device according to claim 5, wherein said first gate circuit comprises:

a first NAND circuit having a first input connected to said row decoder and a second input for receiving the second control signal; and

a second NAND circuit having a first input connected to an output of said first NAND circuit, a second input for receiving the third control signal and an output connected to said word line, and wherein said second gate circuit comprises;

a third NAND circuit having a first input connected to said column decoder and a second input for receiving said second control signal; and

inverters connected between said third NAND circuit and said output gate.

7. A semiconductor nonvolatile memory device according to claim 5, wherein said bit line level control circuit comprises:

a first transistor, connected between said bit line and a high power source, for separating said bit line from the high power source when the first control signal is applied; and

a second transistor, connected to said bit line, for supplying the predetermined potential when the first control signal is applied.

8. A semiconductor nonvolatile memory device according to claim 5, wherein said timing generator circuit comprises:

a flip-flop circuit connected to an input terminal;

first through seventh delay circuits connected in series, each delay circuit including;

an inverter;

a depletion type MOS transistor connected as a diode to said inverter; and

a capacitor connected between an output of said depletion type MOS transistor and a low power source, each of said first through seventh delay circuits having a first through seventh output, respectively, the first control signal being obtained as a reverse output of said NAND circuit which inputs the second and the fifth output signals of said delay circuits, the third control signal being obtained from the output of a first NOR gate which inputs third and fourth outputs of said timing generator circuit, the second control signal being obtained from the output of said flip-flop circuit, and a recall control signal for controlling the third transfer gate transistor being obtained from a second NOR gate which inputs the fifth and sixth outputs of said delay circuits.

9. A semiconductor nonvolatile memory device according to claim 5, wherein the first control signal is generated while the second control signal is generated, and the third control signal is generated while the first control signal is generated.