Method of self-aligning a trench isolation structure to an implanted well region

• US 4,799,990 A
• Filed: 04/30/1987
• Issued: 01/24/1989
• Est. Priority Date: 04/30/1987
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Koburger, Charles W. III, White, Francis R., Parries, Paul C., Lasky, Jerome B., Kerbaugh, Michael L.
• Primary Examiner(s): Schor, Kenneth M.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/044,374
• Time in Patent Office: 635 Days
• Field of Search: 156/643, 156/648, 156/649, 156/645, 156/636, 437/20, 437/62, 437/67, 437/228, 437/249, 437/924, 437/984
• US Class Current: 438/433
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A method for self-aligning an isolation structure to a diffusion region. A first masking layer is formed on a semiconductor substrate, the first masking layer having at least one aperture sidewall which is substantially perpendicular to the semiconductor substrate. Dopant ions are implanted into the semiconductor substrate through the first masking layer to form a doped region. Sidewall spacers are then defined on the sidewalls of the aperture, and a sidewall image reversal process is carried out such that the sidewall spacers define trench apertures in a masking structure. Finally, isolation trenches are etched into the semiconductor substrate through the masking structure. Alternatively, the implantation step is carried out after the sidewall spacers are defined on the first masking layer.

Claims

1. A process for self-aligning an isolation structure to an implanted region, comprising the steps of:

providing on a surface of a semiconductor substrate, a masking layer having at least one aperture formed therein, said aperture having sidewalls which are substantially perpendicular to the surface of said substrate;

implanting dopant ions into said substrate through said masking layer, so as to form a dopant region in said substrate;

defining sidewall spacers on said sidewalls of said aperture formed in said masking layer;

performing a sidewall image reversal process so that said sidewall spacers define trench apertures in a masking structure formed on said substrate;

etching isolation trenches into said substrate through said masking structure; and

wherein said step of implanting dopant ions is carried out immediately after said step of forming sidewall spacers on said sidewalls of said aperture is performed.

2. A process for self-aligning an isolation structure to an implanted region, comprising the steps of:

providing on a surface of semiconductor substrate, a masking layer having at least one aperture formed therein, said aperture having sidewalls which are substantially perpendicular to the surface of said substrate;

defining first sidewall spacers on said sidewalls of said aperture formed in said masking layer;

implanting dopant ions into a portion of said substrate exposed between said first sidewall spacers, so as to form a diffusion region in said substrate;

defining second sidewall spacers on said first sidewall spacers;

performing a sidewall image reversal process so that said first and second sidewall spacers define trench apertures in a masking structure formed on said substrate; and

etching isolation trenches into portions of said semiconductor substrate exposed by said masking structure.

3. A process as claimed in claim 2, wherein said first and second sidewall spacers are each defined by a process comprising the steps of:

depositing a conformal layer on all exposed surfaces of the substrate and said masking layer; and

anisotropically etching to remove all areas of said conformal layer except portions thereof disposed on said sidewalls of said aperture formed in said masking layer.

4. A process as claimed in claim 3, wherein said conformal layer is composed of silicon nitride.

5. A process as claimed in claim 4 wherein the step of removing said sidewall spacers is performed by exposure to H₃ PO₄.

6. A process as claimed in claim 2, wherein the said sidewall image reversal process comprises the steps of:

removing said masking layer;

forming a second masking layer of a thickness sufficient to cover said sidewall spacers;

removing upper-most portions of said second masking layer to a point where said sidewall spacers are exposed; and

removing said sidewall spacers while leaving the second masking layer substantially undisturbed.

7. A process as claimed in claim 6 wherein the step of removing said second masking layer is performed by using a planarizing process.

8. A process as claimed in claim 6 wherein the step of removing said second masking layer is performed by using a polishing process.

9. A process as claimed in claim 2, further comprising the step of:

placing isolation material in said isolation trenches.

10. A process for self-aligning an isolation structure to a diffusion region formed in a surface of a semiconductor substrate, comprising the steps of:

providing a masking layer on the substrate, said masking layer having at least one aperture formed therein having sidewalls which are substantially perpendicular to the surface of the substrate;

depositing a first conformal layer on all exposed surfaces, including said sidewalls of said aperture;

defining first sidewall spacers by anisotropically etching to remove all portions of said conformal layer except those portions disposed on said sidewalls of said aperture, said first sidewall spacers having side surfaces that are substantially perpendicular to the surface of the semiconductor substrate;

implanting dopant ions into a portion of the semiconductor substrate exposed by said first sidewall spacers, so as to form a diffusion region in the substrate;

depositing a second conformal layer on all exposed surfaces, including said side surfaces of said first sidewall spacers;

defining second sidewall spacers by anisotropically etching to remove all portions of said second conformal layer except for the portions disposed on said side surfaces of said first sidewall spacers;

removing said first masking layer;

forming a second masking layer of a thickness sufficient to cover said first and second sidewall spacers;

planarizing said second masking layer to a point where said first and second sidewall spacers are exposed;

defining trench apertures in said second masking layer by removing said exposed sidewall spacers while leaving said second masking layer substantially undisturbed; and

forming isolation trenches by etching the portions of said semiconductor substrate exposed through said second masking layer.

11. A process as claimed in claim 10 further comprising the step of:

providing isolation material in said isolation trenches.