Multi-plane page mode video memory controller

• US 4,800,380 A
• Filed: 12/21/1982
• Issued: 01/24/1989
• Est. Priority Date: 12/21/1982
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Convergent Technologies, Inc. (Secured Digital Applications, Inc.)
• Inventors: Lowenthal, Richard W., Ramsay, Michael, Reeber, Larke E., Hoffman, Drew S.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/452,000
• Time in Patent Office: 2,226 Days
• Field of Search: 340/750, 340/798, 340/799, 340/703, 340/749, 340/747, 340/802
• US Class Current: 345/570
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A page mode memory controller for a multi-plane color video display providing three bits/pixel corresponding to three page partitioning in each of sixteen 64K dynamic RAMs is described. The three bits/pixel are routed to a color lookup table to provide a choice of eight colors from a palette of 64 colors. Graphic display information is combined with alphanumeric video information on a pixel-by-pixel basis. The combined graphic/alphanumeric information is then converted from a digital signal to an analog signal. Page mode reads access three color planes for video display cycles using a counter for the two least significant memory column address bits. To create the displayed image, vectors are drawn three times, once at each plane.

Claims

1. A page mode memory controller for accessing a dynamic random access memory (RAM), comprising:

means for accessing a selected memory row address;

means for latching said selected memory row address during a memory access interval;

means for providing a selected most significant (MS) memory column address portion;

means for providing a selected least significant (LS) memory column address portion;

means for combining said MS and said LS memory column address portions and for periodically accessing a corresponding memory column address during said memory access interval; and

a counter for sequentially incrementing said LS memory column address portion, in coordination with said periodic memory column address access, wherein a plurality of memory column addresses are accessed during said memory access interval, locating a plurality of corresponding sequential memory pages.

2. The memory controller of claim 1, further comprising:

means for selectably entering data into, and retrieving data from, memory locations defined by an intersection of said memory row and column addresses.

3. The memory controller of claim 2, further comprising an array of RAMs.

4. In a multi-plane video graphic display, a page mode memory controller for accessng a dynamic random access memory (RAM) image memory array, comprising:

a graphics controller for generating in sequence;

(a) a memory row address signal;

(b) a memory row strobe signal, wherein said address signal is latched into each memory element in said image memory array during a memory access period; and

thereafter

(c) a most significant (MS) portion of a memory column address signal;

a counter for generating a least significant (LS) portion of a memory column address signal;

means for combining said MS portion and said LS portion of said memory column address signal;

means for generating a memory column strobe signal at spaced intervals during said memory access period after generation of said memory row strobe signal; and

means for sequentially incrementing said counter coincident with each generation of said memory column strobe signal, wherein a plurality of sequential image memory array pages are accessed during said memory access period, each page corresponding to one of said video display planes.

5. The memory controller of claim 4, further comprising:

means for selectably entering data into, and retrieving data from, memory array locations defined by an intersection of said memory row and column addresses.

6. The memory controller of claim 5, further comprising:

a shift register for sequentialy storing said image memory array pages, one in parallel with the other, during said memory access period, and for subsequently providing a simultaneous serial bit stream output for each of said image memory array pages, each serial bit corresponding to a discrete display pixel location.

7. The memory controller of claim 6, said image memory array comprising a plurality of dynamic RAMs.

8. The memory controller of claim 7, further comprising:

a memory address bus linking said graphics controller and said counter with said memory array and over which said memory row address signal is first provided to said memory array and, thereafter, said memory column address signal is provided to said memory array, during each memory access period.

9. The memory controller of claim 8, each of said video display planes comprising a display color or intensity attribute.

10. The memory controller of claim 9, further comprising:

a color mapper for simultaneously receiving each of said shift register serial output bit streams and for assigning color or intensity attributes to each corresponding display pixel location in accordance therewith.

11. The memory controller of claim 10, further comprising:

means for converting said serial bit streams and corresponding assigned color attributes into an analog video signal.

12. A memory controller of claim 4, said video graphics display further comprising an alphanumeric display.

13. A method for accessing a dynamic random access memory (RAM), comprising:

accessng a selected memory row address;

latching said selected memory row address during a memory access interval;

providing a selected most significant (MS) memory column address portion;

providing a selected least significant (LS) memory column address portion;

combining said selected MS and LS memory column address portions;

periodically accessing a memory column address corresponding to said combined MS and LS memory column address portions during said memory access interval; and

sequentially incrementing said LS address portion in coordination with said periodic memory column address access, wherein a plurality of memory column addresses are accessed during said memory access interval, locating a plurality of corresponding sequential memory pages.

14. The method of claim 13 further comprising:

selectably entering data into, and retrieving data from, memory locations defined by an intersection of said memory row and column addresses.

15. In a multi-plane video graphics display, a method for accessing a dynamic random access memory (RAM) image memory array, comprising:

generating a memory row address signal;

generating a memory strobe signal, wherein said address signal is latched into each memory element in said image memory array during a memory access period;

generating a most significant (MS) portion of a memory column address;

generating a least significant (LS) portion of a memory column address;

combining said MS portion and said LS portion of said memory column address signal;

generating a memory column strobe signal at spaced intervals during said memory access period after generation of said memory row strobe signal; and

sequentially incrementing said LS memory column address signal portion coincident with each generation of said memory column strobe signal, wherein a plurality of sequential image memory array pages are accessed during said memory access period, each page corresponding to one of said video display planes.

16. The method of claim 15, further comprising:

selectably entering data into, and retrieving data from, memory array locations defined by an intersection of said memory row and column addresses.

17. The method of claim 16, further comprising:

sequentially storing said image memory array pages, one in parallel with the other, during said memory access period; and

subsequently providing a simultaneous serial bit stream output for each of said image memory pages, each serial bit corresponding to a discrete display pixel location.

18. The method of claim 17, further comprising:

assigning color or intensity attributes to each corresponding display pixel location of said serial bit streams.

19. The method of claim 18, further comprising:

converting said serial bit streams and corresponding assigned color or intensity attributes into an analog video signal.

20. In a multi-plane video graphics display, a method for accessing a dynamic random access memory (RAM) image memory array, comprising:

generating a memory row address signal;

latching said memory row address signal into said memory array with a memory row address strobe signal;

removing said memory row address signal;

generating a first memory column address strobe signal;

generating a most significant portion (MS) of a memory column address signal;

generating a least significant (LS) portion of a memory column address signal;

combining said MS and said LS portions of said memory column address signal;

accessing a first memory array location defined by an intersection of said memory row and column addresses;

storing data contained at said memory array location in a buffer;

removing said first memory column address strobe signal;

incrementing said LS portion of said row address signal;

generating a second memory column address strobe signal;

accessing a second memory location defined by an intersection of said memory row and incremented column addresses;

removing said second memory column address strobe signal; and

serially shifting the data stored in said buffer from said buffer while simultaneously shifting data from said second memory location, to form two bit streams corresponding to a plurality of sequential display pixel locations having color or intensity attributes selected by the combined, multiple bit stream data.

21. The method of claim 20, further comprising:

further incrementing said LS portion of said memory column address signal and subsequently accessing a corresponding memory location a plurality of times, corresponding to a desired number of display planes.