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Multi-plane page mode video memory controller

  • US 4,800,380 A
  • Filed: 12/21/1982
  • Issued: 01/24/1989
  • Est. Priority Date: 12/21/1982
  • Status: Expired due to Term
First Claim
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1. A page mode memory controller for accessing a dynamic random access memory (RAM), comprising:

  • means for accessing a selected memory row address;

    means for latching said selected memory row address during a memory access interval;

    means for providing a selected most significant (MS) memory column address portion;

    means for providing a selected least significant (LS) memory column address portion;

    means for combining said MS and said LS memory column address portions and for periodically accessing a corresponding memory column address during said memory access interval; and

    a counter for sequentially incrementing said LS memory column address portion, in coordination with said periodic memory column address access, wherein a plurality of memory column addresses are accessed during said memory access interval, locating a plurality of corresponding sequential memory pages.

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