Auto sync polarity control circuit for use with monitor

• US 4,800,429 A
• Filed: 03/14/1988
• Issued: 01/24/1989
• Est. Priority Date: 03/14/1988
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Perkins, Geoffrey W.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US07/168,108
• Time in Patent Office: 316 Days
• Field of Search: 358/153, 358/148, 358/150, 358/154, 340/814, 328/139, 328/118, 328/140
• US Class Current: 348/500
• CPC Class Codes: H04N 5/06 Generation of synchronising signals

Abstract

A control circuit for use with personal computer monitors automatically provides single polarity horizontal and vertical sync pulses from either TTL or analog composite sync signals supplied from any of a variety of personal computers. The control circuit has both a vertical and horizontal sub-circuit each including an integrator and an exclusive OR gate wherein the inputs of the latter are coupled respectively to the input and the output of the former. Additionally the vertical sub-circuit includes a second exclusive gate the output of which is coupled to the input of the integrator thereof and whose inputs are respectively coupled to the output of the integrator of the horizontal sub-circuit and an input to which is supplied vertical TTL sync input signals while either horizontal TTL sync or TTL sync input signals are supplied to the input of the horizontal sub-circuit. In operation the control circuit defaults to the analog composite sync input in the absence of TTl horizontal or composite sync input signals. The analog composite circuit separates the horizontal and vertical sync information and applies the same to the integrator of the horizontal sub-circuit.

Claims

1. Circuit for providing single polarity pulses at first and second outputs in response to receiving applied digital input signals, comprising:

first circuit means responsive to either positive or negative applied input signals for providing single polarity pulses at the first circuit output including a first integrator having an input coupled to a first input of the circuit and an output; and

a first gate circuit having an output coupled to the first circuit output, a first input coupled to said input of said first integrator and a second input coupled to said output of said first integrator; and

second circuit means responsive to either negative or positive input signals for providing single polarity pulses at the second circuit output including a second integrator having an input and an output;

a second gate circuit having an output coupled to the second circuit output, a first input coupled to said output of said second integrator, and a second input coupled to said input of said second integrator; and

a third gate circuit having an output coupled to said input of said second integrator, a first input coupled to a second input of the circuit and a second input coupled to said output of said first integrator.

2. The circuit of claim 1 including:

third circuit means having an input coupled to a third input of the circuit to which are supplied analog composite signals for providing corresponding digital output signals and an output coupled both to said output of said first integrator and said first input of said first gate circuit; and

fourth circuit means for enabling said third circuit means while electrically decoupling said input of said first integrator from said first input of the circuit in the absence of digital signals being applied to said first input of the circuit and disabling said third circuit means while electrically coupling said input of said first integrator to said first input of the circuit in the presence of said applied digital signals.

3. The circuit of claim 2 wherein said first, second and third gate circuits are exclusive OR gates.

4. A control circuit for automatically providing horizontal and vertical single polarity sync pulses at respective outputs, comprising:

first circuit means having an input coupled to a first input of the control circuit to which TTL horizontal or composite sync signals are supplied, said first circuit means including a first integrator having an input coupled to said first input of the control circuit and an output, and a first gate circuit having a first input coupled to said output of said first integrator, a second input coupled to said input of said first integrator and an output coupled to a first one of the outputs of the control circuit; and

second circuit means having an input coupled to a second input of the control circuit to which TTL vertical sync signals are supplied, said second circuit means including a second integrator having an input and an output, a second gate circuit having a first input coupled to said second input of the control circuit, a second input coupled to said output of said first integrator and an output coupled to said input of said second integrator, and a third gate circuit having a first input coupled to said output of said second integrator, a second input coupled to said input of said second integrator and an output coupled to a second one of the outputs of the control circuit.

5. The control circuit of claim 4 including:

third circuit means coupled to a third input of the control circuit to which are supplied analog composite sync signals for providing vertical and horizontal sync signals at an output thereof, said output being coupled both to said input of said first integrator and said second input of said first gate circuit; and

detector means having an input coupled to said first input of the control circuit for enabling said third circuit means during operation of the control circuit while electrically decoupling said first circuit means from said first input of the control circuit in the absence of TTL signals applied to said first input of the control circuit and disabling said third circuit means while electrically coupling said first circuit means to said first input of the control circuit when the TTL signals are supplied to said first input of the control circuit.

6. The control circuit of claim 5 wherein said first, second and third gate circuits are exclusive OR gates.

7. The control circuit of claim 5 wherein the rise time of said first integrator is less than the rise time of said second integrator.