Fundamental unit for processing video signals

• US 4,800,430 A
• Filed: 05/30/1986
• Issued: 01/24/1989
• Est. Priority Date: 10/01/1984
• Status: Expired due to Fees

• Current Assignee: Nippon Hoso Kyokai
• Original Assignee: Nippon Hoso Kyokai
• Inventors: Yagi, Nobuyuki, Enami, Kazumasa, Murakami, Keinosuke
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US06/879,108
• Time in Patent Office: 970 Days
• Field of Search: 358/160, 358/181, 358/22, 358/182, 358/183, 358/185, 382/41, 382/49
• US Class Current: 348/721
• CPC Class Codes: H04N 5/262 Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects

Abstract

A video signal processing system having a plurality of units to be operated in parallel with each other. Each unit has an input selector for selecting one video input and output selectors for selecting one video output. The selected video input is initially stored in a memory and is processed in accordance with a program which is stored in another memory in a sequencer to execute a specific video effect. The video signal subject to the video effect is supplied to the output selectors and delivered from the selected output selector. This processing is performed in parallel with respect to the units in accordance with respective programs stored in the respective memories in the respective sequencers.

Claims

1. A fundamental unit for processing video signals, comprising:

(a) video signal selection means, receiving video signals transmitted through a plurality of first transmission lines, for selecting one of the video signals, the selected video signal having a sync signal;

(b) memory means for storing therein the selected video signal;

(c) write control means for controlling said memory means to store the selected video signal as data in said memory means by utilizing the sync signal of said video signal as a control signal;

(d) readout means for addressing said memory means to read out said data from said memory means;

(e) arithmetic means for operating arithmetically on said data read out by said readout means;

(f) output means for outputting, on a respective plurality of second transmission lines, signals selected from the result of the operation of said arithmetic means and the video signals on said first transmission lines; and

(g) programmable control means for controlling said video signal selection means, said readout means, said arithmetic means, and said output means in accordance with the timing of a system sync signal, said programmable control means having a program memory to store a program for predetermined processing of the selected video signal,

wherein said programmable control means includes means for generating a clock signal, and wherein said write control means includes an address counter which counts said clock signal, said address counter being reset by said sync signal of the selected video signal.

2. A video signal processing system, comprising:

a plurality of fundamental units for processing video signals, each fundamental unit including

(a) video signal selection means, receiving video signals transmitted through a plurality of first transmission lines, for selecting one of the video signals, the selected video signal having a sync signal;

(b) memory means for storing therein the selected video signal;

(c) write control means for controlling said memory means to store the selected video signal as data in said memory means by utilizing the sync signal of the selected video signal as a control signal;

(d) readout means for addressing said memory means to read out said data from said memory means;

(e) arithmetic means for arithmetically operating on said data read out by said readout means;

(f) output means for outputting, on a respective plurality of second transmission lines, signals selected from the result of the operation of said arithmetic means and the video signals on said first transmission lines; and

(g) programmable control means for controlling said video signal selection means, said readout means, said arithmetic means, and said output means in accordance with the timing of a system sync signal, said programmable control means having a program memory to store a program for predetermined processing of the selected video signal,

wherein the plurality of fundamental processing units are serially connected such that the plurality of second transmission lines of one of the units are respectively connected to the plurality of first transmission lines of the next one of the units.

3. A video signal processing system as claimed in claim 2, wherein said programmable control means comprises means for generating a clock signal, and wherein said write control means comprises an address counter which counts said clock signal, said address counter being reset by said sync signal of the selected video signal.

4. A video signal processing system as claimed in claim 3, wherein said write control means comprises a horizontal address counter and a vertical address counter, each of said counters having a respective countup input and a respective clear input;

wherein the sync signal of the selected video signal includes a horizontal sync signal and a vertical sync signal;

wherein the programmable control means comprises means for generating a clock signal;

wherein said clock signal is applied to the countup input of said horizontal address counter;

wherein the horizontal sync signal is applied to the reset input of said horizontal address counter and to the countup input of said vertical address counter; and

wherein the vertical sync signal is applied to the reset input of said vertical address counter.

5. A video signal processing system as claimed in claim 2, wherein said readout means comprises an arithmetic logic unit.

6. A video signal processing system as claimed in claim 2, wherein said arithmetic means comprises an arithmetic logic unit.

7. A video signal processing system as claimed in claim 2, wherein said output means selectively passes said data read out from said memory means and said video signals on said first transmission lines under the control of said programmable control means.

8. A fundamental unit for processing video signals, comprising:

(a) video signal selection means, receiving video signals transmitted through a plurality of first transmission lines, for selecting one of the video signals, the selected video signal having a sync signal, the sync signal of the selected video signal including a horizontal sync signal and a vertical sync signal;

(b) memory means for storing therein the selected video signal;

(c) write control means for controlling said memory means to store the selected video signal as data in said memory means by utilizing the sync signal of said video signal as a control signal, said write control means including a horizontal address counter and a vertical address counter, each of said counters having a respective countup input and a respective clear input;

(d) readout means for addressing said memory means to read out said data from said memory means;

(e) arithmetic means for operating arithmetically on said data read out by said readout means;

(f) output means for outputting, on a respective plurality of second transmission lines signals selected from the result of the operation of said arithmetic means and the video signals on said first transmission lines; and

(g) programmable control means for controlling said video signal selection means, said readout means, said arithmetic means, and said output means in accordance with the timing of a system sync signal, said programmable control means having a program memory to store a program for predetermined processing of the selected video signal, said programmable control means additionally including means for generating a clock signal, said clock signal being applied to the countup input of said horizontal address counter,

wherein the horizontal sync signal is applied to the reset input of said horizontal address counter and to the countup input of said vertical address counter, and wherein said vertical sync signal is applied to the reset input of said vertical address counter.

9. A fundamental unit for processing video signals, comprising:

(a) video signal selection means, receiving video signals transmitted through a plurality of first transmission lines, for selecting one of the video signals, the selected video signal having a sync signal;

(b) memory means for storing therein the selected video signal;

(c) write control means for controlling said memory means to store the selected video signal as data in said memory means by utilizing the sync signal of said video signal as a control signal;

(d) readout means for addressing said memory means to read out said data from said memory means, said readout means including an arithmetic logic unit;

(e) arithmetic means for operating arithmetically on said data read out by said readout means;

(f) output means for outputting, on a respective plurality of second transmission lines one, signal selected from result of the operation of said arithmetic means and the video signals on said first transmission lines; and

(g) programmable control means for controlling said video signal selection means, said readout means, said arithmetic means, and said output means in accordance with the timing of a system sync signal, said programmable control means having a program memory to store a program for predetermined processing of the selected video signal.