Semiconductor nonvolatile memory device

• US 4,800,533 A
• Filed: 04/29/1987
• Issued: 01/24/1989
• Est. Priority Date: 04/30/1986
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Arakawa, Hideki
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/043,791
• Time in Patent Office: 636 Days
• Field of Search: 365/226, 365/228, 365/229, 365/154, 365/190
• US Class Current: 365/228
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A semiconductor nonvolatile memory device includes a plurality of nonvolatile random access memory cells constituted by volatile memory cells and nonvolatile erasable programmable read only memory cells. A sense circuit senses a level of potential of a power source, and based on the sensed level, selects a store operation or a recall operation. Also included are a first terminal for the power source and a second terminal for an auxiliary power source. The detection of a rise or fall of the potential at the first terminal is carried out in the sense circuit and based on the result of the potential detection, a data transmission from the volatile random access memory cell to the nonvolatile erasable programmable read only memory cell or from the nonvolatile erasable programmable read only memory to the volatile random access memory is automatically carried out.

Claims

1. A semiconductor nonvolatile memory device comprising:

a plurality of nonvolatile random access memory cells constituted by volatile memory cells and nonvolatile erasable programmable read only memory cells;

a first terminal for receiving a power source voltage;

a second terminal for receiving an auxiliary power source voltage;

a sense circuit, connected to said first terminal, monitoring said power source voltage to generate both a first control signal, when the power source voltage reaches a normal range, and a second control signal, when the power source voltage falls out of the normal range;

first switch means, connected between said first and second terminals, for supplying the power source voltage to said second terminal;

second switch means, connected between said first terminal and said nonvolatile random access memory cells, for supplying the power source voltage;

third switch means, connected between said second terminal and said nonvolatile random access memory cells, for supplying the auxiliary power source voltage; and

control means, connected to said nonvolatile random access memory cells, said second switch means, and said sense circuit, for recalling data stored in the nonvolatile erasable programmable read only memory cells to the volatile memory cells in response to the first control signal and for storing data stored in the volatile memory cells to the nonvolatile memory erasable programmable read only memory cells in response to the second control signal, wherein said first and second switch means are turned off when the power source voltage falls down, and said third switch means is turned on in response to said second control signal.

2. A semiconductor nonvolatile memory device according to claim 1, wherein said first switch means include a first transistor, connected between said first and second terminals, having a gate connected to said first terminals;

said second switch means include a second transistor, connected between said first terminal and said nonvolatile random access memory cells, having a gate connected to said first terminal; and

said third switch means includes a third transistor, connected between said second terminal and said nonvolatile random access memory cells, having a gate connected to said control means.

3. A semiconductor nonvolatile memory device comprising:

a memory cell array portion having a plurality of nonvolatile memory cells and a plurality of volatile memory cells;

a first terminal for receiving a power source voltage;

a second terminal for receiving an auxiliary power source voltage;

sense circuit means, connected to said first terminal, for generating a first control signal when the power source voltage is larger than a first predetermined voltage, and generating a second control signal when the power source voltage is smaller than a second predetermined voltage;

control circuit means, connected to said sense circuit means and said memory cell array portion, for controlling a data transfer from the nonvolatile memory cells to the volatile memory cells in response to the first control signal and a data transfer from the volatile memory cells to the nonvolatile memory cells in response to said second control signal; and

switching means, connected to said first and second terminals and said memory cell array portion, for supplying the auxiliary power source voltage instead of the power source voltage to said memory cell array portion in response to the second control signal.

4. A semiconductor nonvolatile memory device according to claim 3, wherein the first predetermined voltage is larger than the second predetermined voltage.

5. A semiconductor nonvolatile memory device according to claim 3, wherein said switching means comprises a first transistor connected between said first terminal and said second terminal, a second transistor connected between said first terminal and said memory cell array portion, and a third transistor, connected between said second terminal and said memory cell array portion, said third transistor being turned on in response to the second control signal.

6. A semiconductor nonvolatile memory device according to claim 5, wherein said control circuit means comprises a voltage booster circuit activated by the second control signal for generating a boosted signal to turn on the third transistor.

7. A semiconductor nonvolatile memory device according to claim 5, wherein said switching means comprises a first transistor connected between said first terminal and said memory cell array portion, and a terminal second transistor, connected between said second terminal and said memory cell array portion, said second transistor being turned on in response to the second control signal.

8. A semiconductor nonvolatile memory device according to claim 7, wherein said control circuit means comprises a voltage booster circuit activated by the second control signal for generating a boosted signal to turn on the second transistor.