Chip separation and alignment apparatus

• US 4,801,044 A
• Filed: 05/27/1987
• Issued: 01/31/1989
• Est. Priority Date: 05/27/1986
• Status: Expired due to Term

• Current Assignee: Nitto Kogyo KK (NEPRO JAPAN)
• Original Assignee: Nitto Kogyo KK (NEPRO JAPAN)
• Inventors: Kubo, Masahiro, Kubota, Shigeru, Kanou, Shoji
• Primary Examiner(s): Rolla, Joseph J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/054,497
• Time in Patent Office: 615 Days
• Field of Search: 221/278, 221/168, 221/163, 221/200, 221/202, 221/156, 221/233, 221/264, 221/197, 366/101, 366/106, 366/107, 406/137, 406/136, 406/138, 406/88
• US Class Current: 221/163
• CPC Class Codes: B65G 47/1407 the articles being fed from a container, e.g. a bowl
• CPC Class Codes: H05K 13/027 Fluid transport of components

Abstract

A chip separation and alignment apparatus capable of accurately and readily accomplishing separation and alignment of chips with a simple construction. The apparatus includes a chip separation and alignment section and a chip separation section. The chip separation and alignment section includes a chip cassette formed into a flat rectangular box-like shape, in which are formed a chip storage chamber, a chip alignment hole provided with an upper end opening through which the chip alignment hole is communicated with a lower portion of the chip storage chamber and a lower end opening, and at least one air ejection port arranged near the upper end opening to intermittenly eject air therethrough. The chip separation section is arranged at the lower end opening of the chip alignment hole to separate chips one by one and to successively supply the separated chips to a subsequent step.

Claims

1. A chip separation and alignment apparatus comprising:

(a) a principal chip storage chamber which, in use, contains a relatively large number of chips, said principal chip storage chamber having at least one air purge hole therein near the top thereof;

(b) a secondary chip storage chamber which, in use, contains a relatively small number of chips, and secondary chip storage chamber being located beneath said principal chip storage chamber and being separated therefrom by a gate that defines the lower opening of a passageway sized and shaped to permit a small number of chips to pass abreast from said principal chip storage chamber to said secondary chip storage chamber;

(c) first means for intermittently introducing blasts of pressurized air into said secondary chip storage chamber so as to scatteringly separate the chips in said secondary and primary chip storage chambers during alternating first periods, after which the chips fall back into the lower portions of said secondary and primary chip storage chambers under the force of gravity during alternating second periods;

(d) a control plate having an upper surface, said control plate being disposed in said secondary chip storage chamber beneath the opening of said passageway into said secondary chip storage chamber and being sized, shaped, and positioned so that its upper surface supports a small number of chips during the alternating second periods and so that said control plate and said gate cooperate to prevent the chips from filling said secondary chip storage chamber during the alternating second periods;

(e) a chip alignment hole projecting downwardly from said secondary chip storage chamber, said chip alignment hole being sized and shaped to pass the chips one after the other in linear array; and

(f) second means for alternatingly blocking the lower end of said chip alignment hole and permitting one of the chips therein to exit said chip alignment hole and pass to a subsequent step.

2. A chip storage and alignment apparatus as recited in claim 1 wherein said first means comprise:

(a) a first air ejection port that communicates with the bottom of said secondary chip storage chamber and

(b) a second air ejection port that communicates with said secondary chip storage chamber adjacent said control plate.

3. A chip storage and alignment apparatus as recited in claim 1 wherein said second means comprise:

(a) a rod disposed at the downstream end of said chip alignment hole;

(b) a groove in said rod sized and shaped to receive a single one of the chips; and

(c) third means for moving said rod back and forth between a first position in which said groove is positioned to receive one of the chips and a second position in which said rod blocks the downstream end of said alignment hole and said groove is positioned so that the chip therein can pass to a subsequent step.