Process for obtaining multiple sheet resistances for thin film hybrid microcircuit resistors

• US 4,801,469 A
• Filed: 08/07/1986
• Issued: 01/31/1989
• Est. Priority Date: 08/07/1986
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: United States Of America As Represented By The Department Of Energy
• Inventors: Norwood, David P.
• Primary Examiner(s): Goldberg, E. A.
• Assistant Examiner(s): Lateef, M. M.
• Application Number:
  US06/894,145
• Time in Patent Office: 908 Days
• Field of Search: 338/306, 338/307, 338/308, 338/309, 338/312, 338/320, 338/314, 29/620, 29/610 R, 118/624, 427/101, 427/102, 427/103, 427/123, 427/125, 427/126.1
• US Class Current: 427/103
• CPC Class Codes: H01C 17/003 using lithography, e.g. photolithography lithographic compositions and processing in general G03F
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: Y10T 29/49099 Coating resistive material on a base

Abstract

A standard thin film circuit containing Ta₂ N (100 ohms/square) resirs is fabricated by depositing on a dielectric substrate successive layers of Ta₂ N, Ti and Pd, with a gold layer to provide conductors. The addition of a few simple photoprocessing steps to the standeard TFN manufacturing process enables the formation of Ta₂ N+Ti (10 ohms/square) and Ta₂ N+Ti+Pd (1 ohm/square) resistors in the same otherwise standard thin film circuit structure.

Claims

1. A process of manufacturing on a surface of a substrate member a thin film network (TFN) circuit including a plurality of resistors formed of materials characterized by different resistivities, said process comprising the steps of:

depositing on said surface of said substrate a first layer comprising tantalum nitride (Ta₂ N) to a first thickness, said Ta₂ N layer having a high resistivity;

depositing on said first layer of Ta₂ N a second layer comprising titanium metal (Ti) to a second thickness, the combined layers of Ta₂ N+Ti having an intermediate resistivity;

depositing on said second layer comprising Ti a third layer comprising palladium metal (Pd) to a third thickness, said combined layers of Ta₂ N+Ti+Pd having a low resistivity;

masking a first portion of said third layer and subsequently plating the remainder of said third layer with gold to form a plurality of conductive paths;

masking a second portion of said third layer and said conductive paths, and subsequently removing the remainder of both said third layer and said second layer to expose said first layer thereunder said masked second portion defining said low resistivity resistor between two conductive paths;

masking said low conductivity resistor, said conductive paths, and a third portion of said first layer exposed by the previous step, and subsequently removing the remainder of said exposed first layer, said masked third portion defining a resistivity resistor between two conductive paths in said TFN circuit.

2. A process according to claim 1, further comprising the step of:

stabilizing said TFN resistors on said substrate by maintaining it in air at a temperature of approximately 300°

C. for approximately two hours.

3. A process according to claim 1, wherein:

said first thickness of said first layer comprising Ta₂ N is in the range 400 Å

-1200 Å

.

4. A process according to claim 3, wherein:

said second thickness of said second layer comprising Ti is approximately 2000 Å

; and

said third thickness of said third layer comprising Pd is approximately 2000 Å

.

5. A process according to claim 4, wherein:

said pattern plating of gold provides a gold plating thickness in the range 3-6 microns.

6. A process of manufacturing on a surface of a substrate a thin film network (TFN) circuit including a plurality of resistors formed of materials characterized by having, respectively, low, intermediate and high resistivities, said process comprising the steps of:

depositing on said surface of said substrate a first layer comprising tantalum nitride (Ta₂ N) to a first thickness, said Ta₂ N layer having said high resistivity;

depositing on said first layer of Ta₂ N a second layer comprising titanium metal (Ti) to a second thickness, the combined layers of Ta₂ N+Ti having said intermediate resistivity;

depositing on said second layer comprising Ti a third layer comprising palladium metal (Pd) to a third thickness, said combined layers of Ta₂ N+Ti+Pd having said low resistivity;

masking an area of said third layer and subsequently plating the remainder of said third layer with gold to form a plurality of conductive paths;

masking said conductive paths and said third layer over a first portion of said area, and subsequently removing the remainder of said third layer to expose said second layer thereunder, said masked first portion defining said low resistivity resistor between two conductive paths;

masking said low conductivity resistor, said conductive paths, and said exposed second layer over a second portion of said area, and subsequently removing the remainder of said exposed second layer to expose said first layer thereunder, said masked second portion defining said intermediate resistivity resistor between two conductive paths; and

masking said intermediate and low resistivity resistors, said conductive paths, and said exposed first layer over a third portion of said area, and subsequently removing the remainder of said exposed first layer, said masked third portion defining said high resistivity resistor between two conductive paths.

7. A process according to claim 6, further comprising the step of:

stabilizing said TFN resistors on said substrate by maintaining it in air at a temperature of approximately 300°

C. for approximately two hours.

8. A process according to claim 6, wherein:

said first thickness of said first layer comprising Ta₂ N is in the range 400 Å

-1200 Å

.

9. A process according to claim 8, wherein:

said second thickness of said second layer comprising Ti is approximately 2000 Å

; and

said third thickness of said third layer comprising Pd is approximately 2000 Å

.

10. A process according to claim 9, wherein:

said pattern plating of gold provides a gold plating thickness in the range 3-6 microns.