Sample hold circuit
First Claim
1. A sample hold circuit for sampling an analog input signal by use of a sampling pulse having a predetermined sampling frequency and holding and outputting the sampled level of said analog input signal for a predetermined period, said sample hold circuit comprising:
- (a) mode selecting means for selecting one of a hold mode and a follow mode in response to said sampling pulse, said analog input signal being inputted via an input terminal and sampled in response to said sampling pulse, an output signal which follows said analog input signal being outputted therefrom in response to selection of said follow mode by said sampling pulse, wherein the mode selecting means includes a variable gain voltage-to-current converting means which converts an input voltage of said analog input signal into a current corresponding to the level of the input voltage and outputs the converted current as said output signal, the conversion gain of the converting means being determined in accordance with the level of the sampling pulse; and
(b) an integration circuit means for holding and outputting the output signal of said mode selecting means via an output signal terminal, sampled level of said analog input signal being outputted from the integration circuit means in response to selection of said hold mode by said sampling pulse.
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Accused Products
Abstract
A sample hold circuit consists of a variable gain voltage-to-current converter and an integration circuit which are connected in series. The conversion gain of the variable gain voltage-to-current converter varies in response to a level of a sampling pulse and one of a follow mode and a hold mode is selected in response to the level of the sampling pulse. In the follow mode when the level of the sampling pulse is high, the conversion gain of the converter is set to the maximum and an output signal of the integration circuit follows up an analog input signal which is inputted into the converter. In the hold mode when the level of the sampling pulse is low, the conversion gain of the converter is set to the minimum and the level of the output signal of the integration circuit is held at a level just before the hold mode is selected.
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Citations
7 Claims
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1. A sample hold circuit for sampling an analog input signal by use of a sampling pulse having a predetermined sampling frequency and holding and outputting the sampled level of said analog input signal for a predetermined period, said sample hold circuit comprising:
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(a) mode selecting means for selecting one of a hold mode and a follow mode in response to said sampling pulse, said analog input signal being inputted via an input terminal and sampled in response to said sampling pulse, an output signal which follows said analog input signal being outputted therefrom in response to selection of said follow mode by said sampling pulse, wherein the mode selecting means includes a variable gain voltage-to-current converting means which converts an input voltage of said analog input signal into a current corresponding to the level of the input voltage and outputs the converted current as said output signal, the conversion gain of the converting means being determined in accordance with the level of the sampling pulse; and (b) an integration circuit means for holding and outputting the output signal of said mode selecting means via an output signal terminal, sampled level of said analog input signal being outputted from the integration circuit means in response to selection of said hold mode by said sampling pulse. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification