Semiconductor defect monitor for diagnosing processing-induced defects

• US 4,801,869 A
• Filed: 04/27/1987
• Issued: 01/31/1989
• Est. Priority Date: 04/27/1987
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sprogis, Edmund J.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/042,906
• Time in Patent Office: 645 Days
• Field of Search: 324/73 R, 324/158 R, 324/528, 324/527, 371/21, 365/201
• US Class Current: 714/733
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

A semiconductor-processing defect monitor construction for diagnosing processing-induced defects. The semiconductor-processing defect monitor utilizes an array layout and includes continuity defect monitoring structures and short-circuit defect monitoring structures. Once a defect has been indicated by a testing operation, the array layout associated with the defect monitor can be used quickly to determine the approximate location of the known defect, thereby facilitating prompt visual observation of the known defect and, thus, prompt determination of the appropriate corrective action to be applied before substantial continued manufacturing has occurred.

Claims

1. A semi-conductof-processing defect monitor comprising:

a conductive line;

a plurality of column lines connectable to column decoder circuitry;

a plurality of row lines connectable to row decoder circuitry; and

a plurality of test cells, each respective test cell being provided at a different location along the length of said conductive line, each said respective test cell comprising transistor means connected to said conductive line and to a different combination of one of said row lines and one of said column lines, such that said row lines, said column lines and said transistor means of said test cells are used to facilitate selective electrical access to different lengths of said conductive line.

2. A semiconductor-processing defect monitor comprising:

a conductive line;

a plurality of column lines connectable to column decoder circuitry;

a plurality of row lines connectable to row decoder circuitry; and

a matrix of test cells arranged in columns and rows, each individual test cell comprising transistor means connected to a different combination of one of said column line and one of said row lines, and to a different location along the length of the conductive line, such that said column line, said row line, and said transistor means are used to facilitate selective electrical access to a different length of said conductive line.

3. A semiconductor-processing defect monitor comprising:

a plurality of cells arranged in columns and rows, each of said cells including first and second serially connected transistors, each transistor having first and second current-carrying electrodes and a control electrode;

a first plurality of conductive lines, a respective one of said lines being connected to the control electrode of each of said first transistors in a column;

a second plurality of conductive lines, a respective one of said second lines being connected to one of said current-carrying electrodes of each of said first transistors in a row;

a third conductive line connected to one of said current-carrying electrodes of at least a portion of said second transistors; and

a fourth conductive line connected to the control electrode of at least a portion of said second transistors.

4. A semiconductor-processing defect monitor as set forth in claim 3 wherein said transistors are field effect transistors.

5. A semiconductor-processing defect monitor as set forth in claim 3, further comprising a column decoder connected to said first plurality of conductive lines and a row decoder connected to said second plurality of conductive lines.

6. A semiconductor-processing defect monitor as set forth in claim 3, wherein each of said cells further comprise a fifth conductive line connected at one end to the common point between said first and second transistors and arranged parallel to one of said first, second, third and fourth lines.

7. A semiconductor-processing defect monitor as set forth in claim 3, wherein each of said cells further includes a fifth plurality of conductive lines, each respective one of said fifth plurality of conductive lines being connected at one end to the common point between said first and second transistors and arranged parallel to one of said first, second, third and fourth lines.

8. A semiconductor-processing defect monitor as set forth in claim 7, wherein each of said respective conductive lines of said fifth plurality is made of the same material as the one of said first, second, third and fourth conductive lines with which it is arranged in parallel.

9. A semiconductor-processing defect monitor as set forth in claim 8, wherein said first plurality of conductive lines are polysilicon lines, said third conductive line is a semiconductor diffusion line and said fourth conductive line is a metallic line.

10. A semiconductor-processing defect monitor comprising:

a matrix of test cells arranged in columns and rows, each of said test cells comprising a test node;

a plurality of column lines connectable to column decoder circuitry;

a plurality of row lines connectable to row decoder circuitry;

first transistor means in each of said test cells, said first transistor means being connected to one of said column lines, to one of said row lines, and to said test node of the respective test cell, such that said row line, said column line and said first transistor means are used to selectively access the test node of each of said test cells;

a first and a second conductive line provided in close proximity to the individual test cells of at least a portion of said matrix; and

second transistor means in the individual test cells of at least a portion of said matrix, said second transistor means being connected to said first and second conductive lines and to said test node of the respective test cell, such that said first and second conductive lines and said second transistor means are used to provide access to the test nodes of the test cells of at least a portion of said matrix.

11. A semiconductor-processing defect monitor as claimed in claim 10, further comprising a third conductive line connected to the test node of each of said test cells, a portion of the length of said third conductive line being constructed parallel to one of said column, row, first and second conductive lines.

12. A semiconductor-processing defect monitor as claimed in claim 10, further comprising third, fourth, and fifth conductive lines connected to the test node of each of said test cells, a portion of the length of said third, fourth and fifth conductive lines being parallel to said row, first and second conductive lines, respectively.

13. A semiconductor-processing defect monitor as claimed in claim 11, wherein said third conductive line is additionally constructed on the same planar level and of the same material as the one of said column, row, first and second conductive lines to which it is parallel.

14. A semiconductor-processing defect monitor as claimed in claim 12, wherein said third, fourth, and fifth conductive lines are additionally constructed on the same planar level and of the same material as said row, first and second conductive lines, respectively.

15. A semiconductor-processing defect monitor as claimed in claim 10, wherein said plurality of column lines are connected to said column decoder circuitry, and said plurality of row lines are connected to said row decoder circuitry.

16. A semiconductor-processing defect monitor as claimed in claim 10, additionally comprising contact test pads connected to the ends of said column lines, row lines, and first and second conductive lines to facilitate electrical connection to said semiconductor-processing defect monitor.