Digitally controlled phase locked loop system

• US 4,802,009 A
• Filed: 07/13/1987
• Issued: 01/31/1989
• Est. Priority Date: 07/13/1987
• Status: Expired due to Term

• Current Assignee: RCA Corporation (General Electric Company)
• Original Assignee: RCA Licensing Corporation
• Inventors: Hartmeier, Werner N.
• Primary Examiner(s): Chin, Tommy P.
• Application Number:
  US07/072,935
• Time in Patent Office: 568 Days
• Field of Search: 358/195.1, 358/11, 358/140, 358/158, 358/148, 358/188, 358/159, 375/97, 375/111, 375/119, 375/120, 328/133, 331/17, 331/25
• US Class Current: 348/537
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0994 comprising an accumulator
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

A phase locked loop system for generating a line-locked clock signal for a television signal processing system includes an analog phase-locked loop nested within a digital phase locked loop. The analog phase-locked loop is synchronized to a reference signal which is derived from the most significant bit of a digital oscillator signal generated by a clocked digital oscillator. To reduce instability in this reference signal, the ratio of the frequency of the clock signal to the frequency of the digital oscillatory signal is chosen to be a noninteger value greater than two. In one embodiment of the invention the stability of the reference signal is further enhanced by adaptively delaying transitions in the reference signal by amounts of time that are inversely proportional to the value of the less significant bits of the samples corresponding to the transitions.

Claims

1. Apparatus comprising:

a variable oscillator, responsive to a control signal for generating an oscillatory signal having a frequency determined by the value of said control signal;

digital signal generation means including a digital oscillator for generating a plural-bit sampled data digital oscillatory signal having a frequency which approximates a predetermined nominal frequency;

phase comparison means, coupled to said variable oscillator and to said digital signal generation means for generating a phase difference signal proportional to the difference in phase between said oscillatory signal and a single-bit digital signal representing a predetermined bit of said plural-bit sampled data digital oscillatory signal; and

means, coupled to said phase comparison means and responsive to said phase difference signal for generating said control signal.

2. The apparatus set forth in claim 1 wherein:

said digital signal generation means further includes;

a source of reference signal having a frequency which approximates a predetermined frequency;

further phase comparison means, coupled to said source of reference signal and to said variable oscillator for generating a further phase difference signal proportional to the difference in phase between said reference signal and said oscillatory signal; and

means, coupled to said further phase comparison means and responsive to said further phase difference signal for generating a further control signal which is applied to said digital oscillator to control the frequency of the plural-bit digital oscillatory signal provided thereby.

3. The apparatus set forth in claim 2 wherein;

said digital signal generation means further includes a source of clock signal having a predetermined frequency;

said digital oscillator is responsive to said clock signal for generating samples of said plural-bit sampled data digital oscillatory siganl at instants determined by said clock signal; and

the ratio of the frequency of said clock signal to the nominal frequency of said plural-bit sampled data digital oscillatory signal is a noninteger value greater than two.

4. The apparatus set forth in claim 3 wherein said digital signal gneration means further includes:

means, coupled to said digital oscillator for generating said single-bit digital signal representing said predetermined bit of said plural-bit sampled data digital oscillatory signal including means for delaying the occurrence of transitions in the value of the predetermined bit of said plural-bit sampled data digital oscillatory signal by respective amounts of time that are inversely proportional to the respective values represented by bits having less significance than said predetermined bit, of respective samples of said sampled data digital oscillatory signal representing the transitions in the value of said predetermined bit.

5. In a television signal processing system, apparatus comprising:

a source of television signals including a horizontal line synchronizing signal component;

signal separation means, coupled to said source, for separating the horizontal line synchronizing signal component from said television signals;

first phase comparison means, coupled to said signal separation means for generating a first phase difference signal representing the difference in phase between said separated horizontal line synchronizing signal and a first oscillatory signal;

means, coupled to said first phase comparison means and responsive to said first phase difference signal for generating a first frequency control signal;

digital signal generation means including a digital oscillator responsive to said first frequency control signal for generating a plural-bit sampled data digital oscillatory signal having a frequency which varies about a nominal frequency by amounts determined by said first frequency control signal;

second phase comparison means, coupled to said digital signal generation means for generating a second phase difference signal representing the difference in phase between a single-bit digital signal, representing a predetermined bit of said plural-bit sampled-data digital oscillatory signal, and a second oscillatory signal;

means, coupled to said second phase comparison means and responsive to said second phase difference signal for generating a second frequency control signal;

a variable oscillator, responsive to said second frequency control signal for generating an analog oscillatory signal having a frequency determined by said second frequency control signal; and

frequency dividing means coupled to said variable oscillator for dividing the analog oscillatory signal provided thereby in frequency by first and second predetermined factors to generate said first and second oscillatory signals.

6. The apparatus set forth in claim 5 wherein:

said digital signal generation means further includes a source of clock signal having a predetermined frequency;

said digital oscillator is responsive to said clock signal for generating samples of said plural-bit sampled data digital oscillatory signal at instants determined by said clock signal; and

the ratio of the frequency of said clock signal to the nominal frequency of said plural-bit sampled data digital oscillatory signal is a noninteger value greater than two.

7. The apparatus set forth in claim 6 wherein said digital signal generation means further includes:

means, coupled to said digital oscillator for generating said single-bit digital signal representing the predetermined bit of said plural-bit sampled data digital oscillatory signal including means for delaying the occurrence of transitions in the value of the predetermined bit of said plural-bit sampled data digital oscillatory signal by respective amounts of time that are inversely proportional to the respective values represented by bits having less significance than said predetermined bit, of respective samples of said sampled data digital oscillatory signal representing the transitions in the value of said predetermined bit.