Decoding apparatus
First Claim
1. A decoding apparatus for decoding input data which was error correction coded, comprising:
- memory means for storing data;
writing means for writing said input data into said memory means;
detecting means supplied with said input data for detecting a write address having a first predetermined numerical magnitude and supplying the detected write address to the writing means to cause it to write the input data into said memory means at the detected write address;
decoding means for producing a decoding address having a second predetermined numerical magnitude, reading out the data stored in said memory means at said decoding address, and decoding the read out data;
comparing means for comparing the numerical magnitude of said write address with that of said decoding address; and
control means connected to said comparing means and said writing means for inhibiting the writing means from writing the input data into said memory means when it is detected by said comparing means that the numerical magnitude of the decoding address is not less than that of said write address.
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Accused Products
Abstract
A decoding apparatus in which the operation to write error correction coded data into a memory and a decoding processing operation of the data read out of the memory are executed in parallel. This decoding apparatus comprises: a comparator for comparing the address to write the data into the memory with the address in the memory for the decoding processing operation; and control means for inhibiting the writing operation when it is detected by the comparator that the decoding processing operation is precedent to the writing operation. With this apparatus, the data which was subjected to the correcting process is prevented from being rewritten into the memory and the pointer derived by the decoding process from being broken.
24 Citations
7 Claims
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1. A decoding apparatus for decoding input data which was error correction coded, comprising:
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memory means for storing data; writing means for writing said input data into said memory means; detecting means supplied with said input data for detecting a write address having a first predetermined numerical magnitude and supplying the detected write address to the writing means to cause it to write the input data into said memory means at the detected write address; decoding means for producing a decoding address having a second predetermined numerical magnitude, reading out the data stored in said memory means at said decoding address, and decoding the read out data; comparing means for comparing the numerical magnitude of said write address with that of said decoding address; and control means connected to said comparing means and said writing means for inhibiting the writing means from writing the input data into said memory means when it is detected by said comparing means that the numerical magnitude of the decoding address is not less than that of said write address. - View Dependent Claims (2)
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3. A decoding apparatus for decoding input data which was divided into predetermined intervals and subjected to a plurality of error correction coding processes, comprising:
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memory means; writing means for writing said input data into the memory means; and first decoding means for decoding the divided input data, using a first code, in parallel during the time interval when said data is being written into the memory means. - View Dependent Claims (4, 5, 6, 7)
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Specification