Buffer memory

• US 4,803,616 A
• Filed: 09/30/1985
• Issued: 02/07/1989
• Est. Priority Date: 10/01/1984
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited (Hitachi, Ltd.)
• Inventors: Uchiyama, Kunio, Hasegawa, Atsushi, Nishimukai, Tadahiko
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US06/781,512
• Time in Patent Office: 1,226 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/52
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array

Abstract

In a buffer memory, a validity flag to be added to each data portion is stored in a tag array or address section at a location corresponding to each data portion. After determining whether each validity flag is to be used as a search object, based upon the data portion to be accessed during searching the tag array and an access mode, the address and its validity flag are simultaneously searched. The logical sum of each output of the search result on a word coincidence line becomes a hit judgement signal.

Claims

1. A buffer memory system comprising:

(1) a data array having a plurality of word lines, and means for storing a plurality of data blocks on each of said plurality of word lines;

(2) a tag array having a plurality of word coincidence lines each of which is connected to a respective one of said plurality of word lines of said data array, said tag array having a first area which stores upper bits of address data of one of a plurality of data blocks in a main memory, said first area having first means for selecting one of said plurality of word coincidence lines so as to read out at least one of said plurality of data blocks from one of said plurality of word lines corresponding to said selected one of said plurality of word coincidence lines, and said tag array having a second area which stores a plurality of validity flags along each of said plurality of word coincidence lines, each of said plurality of validity flags along each respective one of said plurality of word coincidence lines corresponding to a respective one of said plurality of data blocks along the respective word line of said data array and means for searching the first and second areas to detect coincidence between said stored upper bits and an address signal supplied as a search input;

(3) mask control means responsive to lower bits of said address signal as well as to a data length signal indicating the length of data blocks to be read out from said array for generating a plurality of mask signals, each mask signal indicating whether a corresponding validity flag in each word coincidence line is to be used or not used as a search object by said searching means, said plurality of mask signals being supplied to said second area of said tag array to mask said validity flags selectively; and

(4) hit judgement means having a plurality of inputs which are connected to said plurality of word coincidence lines of said tag array, said hit judgement means including means for generating a hit signal indicating that a requested data is present in said data array when coincidence is detected by said searching means.

2. A buffer memory according to claim 1, wherein said hit judgement circuit includes a circuit for obtaining a logical sum of each on said plurality of word coincidence lines.

3. A processor including a buffer memory system, said buffer memory system comprising:

(1) a data array having a plurality of word lines, and means for storing a plurality of data blocks on each of said plurality of word lines;

(2) a tag array having a plurality of word coincidence lines each of which is connected to a respective one of said plurality of word lines of said data array, said tag array having a first area which stores upper bits of address data of one of a plurality of data blocks in a main memory, said first area having first means for selecting one of said plurality of word coincidence lines so as to read out at least one of said plurality of data blocks from one of said plurality of word lines corresponding to said selected one of said plurality of word coincidence lines, and said tag array having a second area which stores a plurality of validity flags along each of said plurality of word coincidence lines, each of said plurality of validity flags along each respective one of said plurality of word coincidence lines corresponding to a respective one of said plurality of data blocks along the respective word line of said data array and means for searching the first and second areas to detect coincidence between said stored upper bits and an address signal supplied as a search input;

(3) mask control means responsive to lower bits of said address signal as well as to a data length signal indicating the length of data blocks to be read out from said data array for generating a plurality of mask signals, each mask signal indicating whether a corresponding validity flag in each word coincidence line is to be used or not used as a search object by said searching means, said plurality of mask signals being supplied to said second area of said tag array to mask said validity flags selectively; and

(4) hit judgement means having a plurality of inputs which are connected to said plurality of word coincidence lines of said tag array, said hit judgement means including means for generating a hit signal indicating that a requested data is present in said data array when coincidence is detected by said searching means.

4. A processor according to claim 3, wherein said hit judgement circuit includes a circuit for obtaining a logical sum of each on said plurality of word coincidence lines.