Circuit translator

• US 4,803,636 A
• Filed: 09/25/1986
• Issued: 02/07/1989
• Est. Priority Date: 09/27/1985
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited 1479 Josuihoncho Kodaira-Shi Tokyo Japan
• Original Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited
• Inventors: Furihata, Makoto, Watanabe, Toshinori, Horie, Noboru, Nishiyama, Tamotsu, Mori, Fumihiko, Kominami, Yasuo
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US06/911,324
• Time in Patent Office: 866 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/300, 364/900
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: Y10S 706/921 Layout, e.g. circuit, construction

Abstract

In order to translate an original circuit consisting of a set of first devices into a target circuit which consists of a set of second devices different from the first devices, and which has the same functions as the original circuit, provision is made of memory means for storing translation rules in the first devices, translation rules in the second devices, and translation rules between the first devices and the second devices, and translation means which successively refers to these translation rules and translates the original circuit data into the target circuit data via steps that translate the original circuit data into a plurality of intermediate data.

Claims

1. A circuit translator for translating an original circuit constituted by a set of first elements into a logically equivalent target circuit constituted by a set of second elements, comprising:

a first memory section which stores translation rules for translating in the set of said first elements;

a second memory section which stores translation rules for translation in the set of said second elements;

a third memory section which stores translation rules for translation of the set of said first elements into the set of said second elements and

translation means which permits translation rules automatically selected from said first memory section to act upon original circuit data to translate the data into first intermediate data, which permits translation rules automatically selected from said third memory section to act upon said first intermediate data to translate the data into second intermediate data, and which permits translation rules automatically selected from said second memory section to act upon said second intermediate data to translate the data into target circuit data.

2. A circuit translator according to claim 1, wherein the translation rules stored in said first memory section are constituted by connecting relation extracting rules that are used for preparing decision data to determine a connecting relation among the elements of the original circuit and a function produced by the elements in the original circuit, and basic concept extracting rules for extracting basic concepts in the original circuit system, and wherein said translation means selected said connecting relation extracting rules and said basic concept extracting rules, and permits them to act upon the original circuit data to translate said original circuit data into first intermediate data.

3. A circuit translator according to claim 1, wherein translation rules stored in said third memory section are constituted by basic concept translating rules that translate basic elements of translation in the original circuit system into basic elements in the target circuit system.

4. A circuit translator according to claim 1, wherein the translation rules stored in said second memory section are constituted by the target circuit generating rules and the target circuit optimizing rules in the target circuit system, and said translation means selects said target circuit generating rules and permits them to act upon said second intermediate data to form from the second intermediate data the target circuit data logically equivalent to the original circuit, and further selects said circuit optimizing rules, and permits them to act upon said target circuit data to optimize the target circuit.

5. A circuit translator according to any one of claim 2 to 4, wherein said first memory section includes means for holding said decision data, and said translation means generates the first intermediate data from the original circuit data using said decision data, and generates the target circuit data from the second intermediate data.

6. A circuit translator according to claim 4, wherein the translation rules stored in said first memory section are constituted by connecting relation extracting rules that are used for preparing decision data to determine a connecting relation among the elements of the original circuit and a function produced by the elements in the original circuit, and basic concept extracting rules for extracting basic concepts in the original circuit system, wherein translation rules stored in said third memory section are constituted by basic concept translating rules that translate basic elements of translation in the original circuit system into basic elements in the target circuit system;

and wherein said translation means provides priority for said basic concept extracting rules, said basic concept translating rules, said target circuit generating rules, and said target circuit optimizing rules, and successively selects the rules in the order of decreasing priority until suitable rules are found, and permits the rules to act upon the corresponding data.

7. A method of translating an original circuit constituted by a set of first elements into a logically equivalent target circuit constituted by a set of second elements, comprising the steps of:

storing first translation rules for translation of the set of first elements into a first memory section;

storing second translation rules for translation of the set of second elements into a second memory section;

storing third translation rules for translation of the set of said first elements into the set of said second elements;

automatically selecting first translation rules from said first memory section;

translating original circuit data into first intermediate data;

automatically selecting third translation rules from said third memory section;

translating said first intermediate data into second intermediate data using said selected third translation rules;

automatically selecting second translation rules from said second memory section; and

translating said second intermediate data into target circuit data using said selected translation rules.

8. A method according to claim 7, wherein said first translation rules include connecting relation extracting rules and basic concept extracting rules;

and

wherein said step of translating said original circuit data into said intermediate data includes the steps of;

selecting said connecting relation extracting rules for determining a connecting relation among said first elements of said original circuit and a function provided by first elements of said original circuit, and

selecting said basic concept extracting rules for extracting basic concepts in said original circuit.

9. A method according to claim 7, wherein said third translation rules stored in said memory section include basic concept translating rules for translating basic elements in said original circuit system into basic elements in said target circuit system.

10. A method according to claim 7,

wherein said second translation rules stored in said second memory section include target circuit generating rules and circuit optimizing rules for the target circuit system;

and

wherein said step of translating said second intermediate data into said target circuit data includes the steps of,

selecting said target circuit generating rules to translate said second intermediate data into said target circuit data which is logically equivalent to said original circuit data, and

selecting said circuit optimizing rules to optimize said target circuit data.

11. A method according to claim 8, wherein said relation extracting rules are used to prepare decision data which is used to translate said original circuit data into first intermediate data.