Resetting system
First Claim
1. A resetting system in an apparatus provided with a main CPU for controlling the whole apparatus and a plurality of slave CPUs each controlling a respective terminal portion of the apparatus to be controlled, the main CPU and said slave CPUs being connected through a common transmission line through which response data is sent from a particular slave CPU to the main CPU as a result of the main CPU sending a command including an address code to address said particular slave CPU, the system comprising:
- a programming unit provided in the main CPU, including means foroutputting strobe signals at a given period of time,determining the existence of communication errors when the response data is not sent in accordance with a predetermined format, andoutputting a first reset signal when a predetermined number of communication errors are generated in succession;
a watch-dog timer for receiving the strobe signals and outputting a second reset signal upon the absence of said strobe signals;
main CPU reset means for resetting the main CPU in response to the outputting of the second reset signal; and
slave CPU reset means for resetting said plurality of slave CPUs in response to the outputting of either the first reset signal or the second reset signal.
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Accused Products
Abstract
A resetting system including a main CPU for an apparatus, and a slave CPU for controlling a terminal portion of the apparatus in association with a watch-dog timer, wherein the main CPU outputs for a predetermined period of time a strobe signal to be supplied to the watch-dog timer, which outputs a reset signal for resetting both the main CPU and slave CPU when the periodical supplying of strobe signals is stopped, indicating an abnormal state of the main CPU. The slave CPU sends a response data corresponding to a command from the main CPU, whereby the main CPU judges as a communication error a response data not in conformity with a predetermined format and, upon the generation of a number of communication errors in succession, the slave CPU is reset by a reset signal outputted from the main CPU.
72 Citations
8 Claims
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1. A resetting system in an apparatus provided with a main CPU for controlling the whole apparatus and a plurality of slave CPUs each controlling a respective terminal portion of the apparatus to be controlled, the main CPU and said slave CPUs being connected through a common transmission line through which response data is sent from a particular slave CPU to the main CPU as a result of the main CPU sending a command including an address code to address said particular slave CPU, the system comprising:
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a programming unit provided in the main CPU, including means for outputting strobe signals at a given period of time, determining the existence of communication errors when the response data is not sent in accordance with a predetermined format, and outputting a first reset signal when a predetermined number of communication errors are generated in succession; a watch-dog timer for receiving the strobe signals and outputting a second reset signal upon the absence of said strobe signals; main CPU reset means for resetting the main CPU in response to the outputting of the second reset signal; and slave CPU reset means for resetting said plurality of slave CPUs in response to the outputting of either the first reset signal or the second reset signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification