Rearrangeable digital signal space division switching system

• US 4,804,956 A
• Filed: 03/31/1986
• Issued: 02/14/1989
• Est. Priority Date: 03/31/1986
• Status: Expired due to Term

• Current Assignee: Computer Network Technology Corp. (Broadcom, Inc.)
• Original Assignee: General Signal Corporation (SPX Corporation)
• Inventors: Boxall, Frank S.
• Primary Examiner(s): YUSKO, DONALD
• Application Number:
  US06/846,910
• Time in Patent Office: 1,051 Days
• Field of Search: 379/221, 340/825.79, 340/825.8, 370/58, 370/63, 370/64, 370/54
• US Class Current: 340/2.21
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A digital signal space division switching system in which signal blocking to new connections is avoided by rearranging existing connections. The rearrangement is accomplished without disturbing existing traffic and without requiring alternate paths to temporarily support existing traffic on rearranged signal paths. Multiple rearrangements are executed simultaneously.

Claims

1. A digital signal switching system comprising

a multi-stage space-division switched network having N input terminals and M output terminals, said switched network providing a plurality of internal digital signal transmission paths where each stage includes a certain number of switches for normally switching said digital signals between each input and one or more outputs in each stage, each of said internal signal paths connecting one of said input terminals to any one or more of said output terminals through each stage only through said certain number of switches, and

means for simultaneously rearranging in a non-blocking fashion any number of said internal signal paths for each stage of said network where said digital signals are switched only through said certain number of switches without changing their end points and without disturbing the digital signals received at the output terminals of said rearranged paths.

3. The system as in claim 1 including means for regenerating said digital signals flowing over said internal signal paths.

4. A system as in claim 1 wherein said digital signals are synchronous.

5. A system as in claim 1 wherein said digital signals are asynchronous.

6. A system as in claim 1 wherein each of said switches includes selector means associated with each output terminal for establishing a signal path to that output from a selected input, each selector means including first register means for storing a configuration code representing the current address of each of the selected inputs.

7. A system as in claim 6 wherein each of said selector means also includes second register means for entering and storing new configuration codes which will subsequently be transferred to said first register means.

8. A system as in claim 7 including means for sequencing the transfer of said new configuration codes from said second register means into said first register means, whereby a change in the network configuration is accomplished by sequentially changing the configuration of each switching stage in time synchronism with the progress of a digital signal bit through the switching stages.

2. The system as in claim wherein M is equal to N.

9. In a multi-stage space division digital signal switching system having N input terminals and M output terminals with internal digital signal paths through said switched network where each stage includes a certain number of switches for normally switching said digital signals between each input and one or more outputs in each stage, and where each of said paths connects any one of the input terminals to any one or more of the output terminals only through said certain number of switches, the method comprising the steps of

simultaneously rearranging in a non-blocking fashion any number of said internal signal paths for each stage of said network only through said certain number of switches without changing the end points and without disturbing the digital signals received at tho output terminals of the rearranged paths.

10. The method as in claim 9 including the step of regenerating the digital signals flowing over the internal paths.

11. A digital signal switching system operating at a certain network clock rate having successive clock ticks, said system comprising

a multi-stage space-division switched network having N input terminals and M output terminals where each stage has address bits which can be changed on a single clock tick, said switched network providing a plurality of internal digital signal transmission paths, each of said internal signal paths connecting one of said input terminals to any one or more of said output terminals, and

means for simultaneously rearranging in a non-blocking fashion any number of said internal signal paths for each stage of said network without changing their end points and without disturbing the digital signals received at the output terminals of said rearranged paths, including means for changing the address bits in the same stage simultaneously, and means for making successive stage by stage address changes on successive ones of said network clock ticks.

12. A digital signal switching system comprising

a multi-stage space-division switched network having N input terminals and M output terminals where each stage includes register means for holding address bits, said switched network providing a plurality of internal digital signal transmission paths, each of said internal signal paths

connecting one of said input terminals to any one or more of said output terminals, and

means for simultaneously rearranging in a non-blocking fashion any number of said internal signal paths for each stage of said network without changing their end points and without disturbing the digital signals received at the output terminals of said rearranged paths, including means for changing the address bits in the same stage simultaneously, and means for changing the address bits in successive stages in sequential synchronism with the passage of a signal bit through said network.

13. A multi-stage switching system for switching multi-bit digital signals, said system comprising

a space-division switched network having N input terminals and M output terminals, said network providing a plurality of internal transmission paths for digital signals, each of said paths connecting one of said input terminals to any one or more of said output terminals,

means for simultaneously rearranging in a non-blocking fashion said paths for each stage of said network without changing their respective end points, and

means for executing the rearrangement of said paths such that at an output terminal of any such rearranged path the last bit of the digital signal arriving over the old path and the first bit of the digital signal arriving over the new path are equally-delayed adjacent bits of the digital signal applied to the input terminal of said rearranged path.

14. A multi-bit signal switching system comprising

a space-division switched network having N input terminals and M output terminals, said network providing a plurality of internal transmission paths for digital signals, each of said paths connected one of said input terminals to any one or more of said output terminals,

means for simultaneously rearranging in a non-blocking fashion any number of said paths without changing their respective end points for each stage of said network,

means for executing the rearrangement of said paths such that at an output terminal of any such rearranged path the last bit of the digital signal arriving over the old path and the firs bit of the digital signal arriving over the new path are equally delayed adjacent bits of the digital signal applied to the input terminal of that rearranged path whereby the rearrangement is accomplished without disturbing the digital signals flowing over such rearranged paths without requiring temporarily-assigned auxiliary paths to support such signals, and in a time interval no longer than the transit time of a digital signal through the network.

15. A system as in claim 14 wherein said multi-bit signals comprise stuffed bit streams including through traffic digital signals and locally generated overhead bits, and wherein said means for executing include means for executing the rearrangement of said paths without disturbing said digital signals even in one or more of said overhead bits are mutilated in transit.

16. The system as in claim 14 wherein M is equal to N.

17. The system as in claim 14 including means for regenerating said digital signals flowing over said internal signal paths.

18. A system as in claim 14 wherein said digital signals are synchronous.

19. A system as in claim 14 wherein said digital signals are asynchronous.

20. A system as in claim 14 wherein said network is a multi-stage network and wherein each stage includes a certain number of switches for normally switching said digital signals between each input and one or more outputs in each stage, and wherein each of said switches includes selector means associated with each output terminal for establishing a signal path to that output from a selected input, each selector means including first register means for storing a configuration code representing the current address of each of the selected inputs.

21. A system as in claim 20 wherein each of said selector means also includes second register means for entering and storing new configuration codes which will subsequently be transferred to said first register means.

22. A system as in claim 21 including means for sequencing the transfer of said new configuration codes from said second register means into said first register means, whereby a change in the network configuration is accomplished by sequentially changing the configuration of each switching stage in time synchronism with the progress of a digital signal bit through the switching stages.