Semiconductor device having MOSFET and deep polycrystalline silicon region

• US 4,805,008 A
• Filed: 06/22/1987
• Issued: 02/14/1989
• Est. Priority Date: 06/23/1986
• Status: Expired due to Term

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Yao, Kenji, Mihara, Teruyoshi
• Primary Examiner(s): Laroche, Eugene R.
• Assistant Examiner(s): Shingleton, Michael B.
• Application Number:
  US07/064,852
• Time in Patent Office: 603 Days
• Field of Search: 357/42, 357/48, 357/59, 357/47, 357/68
• US Class Current: 257/376
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A semiconductor device such as a CMOS is provided with highly doped polycrystalline silicon regions for preventing undesired operations of parasitic transistors. Each polycrystalline region is extended deeper from a top surface of the silicon chip than source and drain regions of MOS transistors. In a substrate region of each MOS, one polycrystalline region of the same conductivity type as the substrate region is formed near the source region, and connected with said source region so that the polycrystalline region is held equipotential with the source region.

Claims

1. A semiconductor device comprising:

a first semiconductor substrate region of a first conductivity type, formed in a substrate body,

a pair of first source and drain regions of a second conductivity type opposite to said first conductivity type, said first source and drain regions being formed in said first substrate region, and separated from each other by a channel portion of said first substrate region to form a first MOSFET,

a first gate electrode formed above said channel portion of said first substrate region, and insulated from said channel portion by a first gate insulating layer, and

a first highly doped polycrystalline silicon region which is the same conductivity type as said first substrate region, and is formed in said first substrate region so that said first polycrystalline silicon region is in contact with said first substrate region, said first polycrystalline silicon region being deeper than said first source and drain regions, and being connected with said first source region to hold said first polycrystalline silicon region equipotential with said source region.

2. A semiconductor device according to claim 1 wherein said first polycrystalline silicon region is located near said first source region.

3. A semiconductor device according to claim 2 further comprising:

a second semiconductor substrate region of said second conductivity type, one of said first and second substrate regions being formed monolithically in the other of said first and second substrate regions within said substrate body,

a pair of second source and drain regions of said first conductivity type, formed in said second substrate region, and separated from each other by a channel portion of said second substrate region to form a second MOSFET,

a second gate electrode formed above said channel portion of said second substrate region and insulated from said second substrate region by a second gate insulating layer,

a second highly doped polycrystalline silicon region which is the same conductivity type as said second substrate region and is formed in said second substrate region near said second source region, said second polycrystalline region being deeper than said second source and drain regions and being connected with said second source region so that said second polycrystalline region is held equipotential with said second source region.

4. A semiconductor device according to claim 3 further comprising:

a third highly doped polycrystalline silicon region which is the same conductivity type as said first substrate region and is formed in said first substrate region, said third polycrystalline region being located between said first and second MOSFETs, and said first source and drain regions being located between said first and third polycrystalline silicon regions, said third polycrystalline silicon region being deeper than said first source and drain regions, and connected with said first source region so that said third polycrystalline silicon region is held equipotential with said first source region, and

a fourth highly doped polycrystalline silicon region which is the same conductivity type as said second substrate region and is formed in said second substrate region, said fourth polycrystalline region being deeper than said second source and drain regions and connected with said second source region so that said fourth polycrystalline silicon region is held equipotential with said second source region, said second source and drain region being located between said second and fourth polycrystalline silicon regions, said fourth polycrystalline silicon region being located between said first and second MOSFETs.

5. A semiconductor device according to claim 4 wherein said first conductivity type is ah n-type, said second conductivity type is a p-type, and said second substrate region is formed in said first substrate region.

6. A semiconductor device according to claim 5 wherein said substrate body has depressions, and each of said polycrystalline silicon regions is formed by depositing polycrystalline silicon in one of said depressions.

7. A semiconductor device according to claim 3 further comprising a third highly doped polycrystalline silicon region formed between said first and second substrate regions, said third polycrystalline silicon region being deeper than said first source and drain regions and said second source and drain regions.

8. A semiconductor device according to claim 7 wherein a top end of said third polycrystalline silicon region is covered with a field insulating oxide layer.

9. A semiconductor device according to claim 8 wherein said first conductivity type is an n-type, said second conductivity type is a p-type, said second substrate region is formed in said first substrate region, and said third polycrystalline silicon region is said second conductivity type.

10. A semiconductor device according to claim 9 wherein said third polycrystalline silicon region is located between said first and second drain regions of said first and second MOSFETs.

11. A semiconductor device according to claim 10 further comprising a fourth highly doped polycrystalline silicon region formed between said first and second substrate regions, said fourth polycrystalline silicon region being deeper than said second source and drain regions, said second source and drain regions being located between said third and fourth polycrystalline silicon regions.

12. A semiconductor device according to claim 11 wherein said substrate body has depressions, and said third and fourth polycrystalline silicon regions are formed by first boring said depressions in said first substrate region, then forming said second substrate region between said depressions, and finally depositing polycrystalline silicon in said depressions.

13. A semiconductor device according to claim 3 further comprising a highly doped semiconductor underlying substrate layer on which said first and second substrate regions are formed.

14. A semiconductor device according to claim 13 wherein said first substrate region is an epitaxial layer grown on said underlying layer, and said second substrate region is formed in said first substrate region.

15. A semiconductor device according to claim 14 further comprising a third highly doped polycrystalline silicon region formed between said first and second substrate regions.

16. A semiconductor device according to claim 15 wherein each of said polycrystalline silicon region reaches said underlying substrate layer.

17. A semiconductor device according to claim 15 wherein an underlying oxide film is formed between a bottom end of each of said polycrystalline silicon regions and said underlying substrate layer.

18. A semiconductor device according to claim 17 wherein each of said polycrystalline silicon regions has such shape and structure that each of said polycrystalline regions grows upwardly from a substantially entire surface of said underlying oxide film, and each of said polycrystalline silicon regions is formed by growing a polycrystalline structure on said underlying oxide film formed on said underlying substrate layer by a step for growing said epitaxial layer on said underlying substrate layer.

19. A semiconductor device according to claim 1 wherein said first polycrystalline region has an impurity concentration higher than that of said first substrate region.