Method for driving a CCD area image sensor in a non-interlace scanning and a structure of the CCD area image sensor for driving in the same method

• US 4,805,026 A
• Filed: 02/17/1987
• Issued: 02/14/1989
• Est. Priority Date: 02/18/1986
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Oda, Eiji
• Primary Examiner(s): Ng, Jin F.
• Assistant Examiner(s): BRINICH, STEPHEN M
• Application Number:
  US07/014,993
• Time in Patent Office: 728 Days
• Field of Search: 358/213.26, 358/213.27, 358/213.29, 358/213.31, 358/213.22, 357/30 H
• US Class Current: 348/320
• CPC Class Codes: H01L 27/14831 Area CCD imagers
• CPC Class Codes: H04N 25/73 using interline transfer [IT]
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals

Abstract

The invention provides a method for driving a CCD area image sensor. An interline transfer type CCD area image sensor includes a plurality of photo sensors arranged in a plurality of lines. A plurality of vertical shift registers are disposed along one of the lines of photo sensors. A horizontal shift register is formed to receive charges from the vertical shift registers. An output circuit converts the charges transferred through the horizontal shift resistor into electrical signals. The driving method includes the steps of accumulating charges in the photo sensors, transferring charges accumulated in all of the photo sensors to the vertical shift registers, and shifting the transferred charges to the horizontal shift register via the vertical shift registers. The start of charge-shiftings is initiated from the charges in the order of the distances between the transferred position and the photo sensors and the horizontal shift register. The charges received from the vertical shift registers are shifted through the horizontal shift register to an output circuit where the quality of charges reaching the output is converted into an electrical signal. The CCD area image sensor includes at least one shift register circuit for producing shift pulses which perform the above-mentioned operations.

Claims

1. A method for driving a CCD area image sensor including a plurality of photo sensors arranged in a plurality of lines, a plurality of vertical shift registers each disposed along one line of said photo sensors, said vertical shift register having a series of plural number of shift stages, each two of said photo sensors being disposed so as to face one of said shift stages, a horizontal shift register formed to receive charges from said vertical shift registers, an output means for converting charges transferred through said horizontal shift register into electrical signals, and a transferring means for transferring charges accumulated in said photo sensors to said vertical shift registers, the method for driving said CCD area image sensor comprising the steps of:

exposing said photo sensors to an object to be sensed to accumulate charges in said photo sensors;

transferring said charges accumulated in all of said photo sensors to said vertical shift registers;

shifting said transferred charges through said vertical shift registers toward said horizontal shift register, the shift through said vertical shift registers being initiated from charges transferred to said vertical shift register at the shift stage nearest to said horizontal shift register to charges transferred to said vertical shift register at the shift stage farthest from said horizontal shift register in order of distance from said horizontal shift register;

shifting charges shifted to said horizontal shift register therethrough toward said output means; and

converting a quantity of charges shifted to said output means to an electrical signal by said output means.

2. A method for driving a CCD area image sensor as claimed in claim 1, wherein said charges transferred to said vertical shift registers are started shifting through said vertical shift registers after the interval between adjacent charges in said vertical shift register is expanded by shifting said adjacent charges.

3. A method for driving a CCD area image sensor as claimed in claim 1, wherein said charges transferred to said vertical shift register are started shifting said vertical shift registers after adjacent charges in said vertical shift register are shifted to the direction to said horizontal shift register to separate from said charges to be started shifting with a distance corresponding to a half of said shift stage of said vertical shift registers.

4. A method for driving a CCD area image sensor as claimed in claim 1, wherein each of said shift stages of said vertical shift registers has two halves, each having a storage electrode and a barrier electrode, each of said photo sensors being disposed to correspond one of said storage electrodes, and charges accumulated in all the photo sensors being simultaneously transferred to parts under every storage electrode of said vertical shift register.

5. A method for driving a CCD area image sensor as claimed in claim 4, wherein charges transferred to said vertical shift registers are started shifting after charges in a preceding stage in said vertical shift register are shifted to empty toward said horizontal shift register to vacate charges from said parts under adjacent barrier and storage electrodes.

6. A CCD area image sensor comprising;

a plurality of photo sensors arranged in a plurality of lines and accumulating charges in response to incident light;

a plurality of vertical shift registers disposed in parallel with one of said lines of said photo sensors, respectively,

a transfer means for transferring charges accumulated in said photo sensors to said vertical shift registers,

a horizontal shift register disposed at one end of said vertical shift registers and having a plurality of shift electrodes;

a charge-voltage converter converting charges received from said horizontal shift register to a voltage form signal;

a first driving means for driving said vertical shift registers to shift charges transferred to said vertical shift registers to said horizontal shift register, said first driving means including means for delaying successively input pulses applied thereto to produce a plurality of successively delayed pulses and means for applying said successively delayed pulses to said shift electrodes of said vertical shift registers; and

a second driving means for driving said horizontal shift register to shift charges in said horizontal shift register to said charge-voltage converter.

7. A CCD area image sensor as claimed in claim 6, wherein said delaying means includes a cascade connection of a plurality of combinations of a transfer gate and an inverter receiving a signal from said transfer gate, said delayed pulses being produced at output nodes of said inverters.

8. A CCD area image sensor as claimed in claim 6, wherein said vertical shift registers include a plurality of shift stages continuously disposed, said shift stages being made of two halves one of said two halves having a storage electrode, the other of said two halves having a barrier electrode and pairs of said storage and barrier electrodes forming shift electrodes, and each of said photo sensors being disposed to correspond to each of said storage electrodes.

9. A CCD area image sensor as claimed in claim 7, wherein said delayed pulses derived from said output nodes of said inverters are applied to said shift electrodes so that the number of said inverters from an input node receiving said input pulses of said delaying means corresponds to the number of shift electrodes counted from said horizontal shift register.

10. A CCD area image sensor as claimed in claim 9, wherein said shift register further includes switches applying four phase shift pulses to said inverters as input signals under a control of a switching signal when said transfer gates are opened.

11. A CCD area image sensor as claimed in claim 10, wherein said switches are respectively made of a MOS field effect transistor having an electrical path between a source and a drain and a gate, one terminal of said electrical path receiving one of said four phase shift pulses, the other terminal of said electrical path supplying said one of said four phase shift pulses to one of said inverters and said gate receiving said switching signal.