Content addressable memory
First Claim
1. A content addressable memory for storing a plurality of data words and selectively retrieving specified said data words in response to a specification word comprising a plurality of specification characters, said content addressable being adapted for use in a host data processing system, said content addressable memory comprising:
- a plurality of storage sections; and
control bus means for coupling each said storage section to the other said storage sections and to said host data processing system, said control bus means including means for coupling a plurality of control signals to each said storage section and means for coupling a said specification character comprising W binary bits to each said storage section, wherein W is greater than 2 and whereineach said storage section comprises;
data word storing means for storing a said data word comprising a plurality of characters, each said character comprising W binary bits, the number of said characters being greater than 2, said storing means including means for separately selecting each character in said data word, the character so selected being determined by a first one of said control signals;
flag means for specifying one of two states, active or inactive, for said storage section; and
processing means for causing said flag means to specify one of said two states operative in response to said control signals, said specification character, and said selected character, said processing means including;
means for causing said flag means to specify the active state for said storage section operative in response to a second one of said control signals; and
reset means for causing said flag means to specify the inactive state for said storage section operative in response to a third one of said control signals and a specified relationship between said specification character and said selected character,wherein, said bus means further comprises means for determining if any of said flag means specifies the active state, said determining means including means for generating a signal if any of said flag means specifies the active state.
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Abstract
A content addressable memory for storing data words wherein each data word includes one or more characters is disclosed. One or more of the characters stored in said content addressable memory may be retrieved in response to commands from a controller coupled to the content addressable memory. The controller includes command circuitry for generating and coupling a plurality of control signals to the content addressable memory, including control signals defining a specification character. The controller also contains response circuitry for receiving a plurality of response signals from the content addressable memory. These response signals include signals specifying a character stored in the content addressable memory. The content addressable memory is constructed from a plurality of storage sections. Each storage section includes control bus coupling circuitry for coupling that storage section to the controller and to the other storage sections. Each storage section also includes circuitry for storing one data word and circuitry for separately selecting each character of the data word so stored. Each storage section may be in one of two states, active or inactive, specified by circuitry contained therein. Each storage section also includes processing circuitry for processing the selected character in response to the control signals. The processing employed is specified by on the control signals, the selected character, the state of the storage section, the specification character, and whether or not the storage section is the first active storage section.
45 Citations
55 Claims
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1. A content addressable memory for storing a plurality of data words and selectively retrieving specified said data words in response to a specification word comprising a plurality of specification characters, said content addressable being adapted for use in a host data processing system, said content addressable memory comprising:
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a plurality of storage sections; and control bus means for coupling each said storage section to the other said storage sections and to said host data processing system, said control bus means including means for coupling a plurality of control signals to each said storage section and means for coupling a said specification character comprising W binary bits to each said storage section, wherein W is greater than 2 and wherein each said storage section comprises; data word storing means for storing a said data word comprising a plurality of characters, each said character comprising W binary bits, the number of said characters being greater than 2, said storing means including means for separately selecting each character in said data word, the character so selected being determined by a first one of said control signals; flag means for specifying one of two states, active or inactive, for said storage section; and processing means for causing said flag means to specify one of said two states operative in response to said control signals, said specification character, and said selected character, said processing means including; means for causing said flag means to specify the active state for said storage section operative in response to a second one of said control signals; and reset means for causing said flag means to specify the inactive state for said storage section operative in response to a third one of said control signals and a specified relationship between said specification character and said selected character, wherein, said bus means further comprises means for determining if any of said flag means specifies the active state, said determining means including means for generating a signal if any of said flag means specifies the active state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 42, 43, 54, 55)
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30. The content addressable memory of 28 wherein said readout means comprises a plurality of gate means for coupling each of said data bus conductors to the corresponding conductor in said specification character coupling means, each said gate means being responsive to the coincidence of said first active signal and a readout control signal comprising one of said control signals.
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41. The content addressable memory of 40 wherein said processing means further comprises means for comparing the signal on each data bus conductor in said data bus means to the signal on the corresponding conductor in said specification character coupling means and means for causing said flag means to specify the inactive state for said storage section if the signal on one of said data bus conductors does not match the signal on the corresponding conductor in said specification character coupling means.
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44. The content addressable memory of 15 wherein an order is defined for the characters stored in said content addressable memory, said order defining comparison relationships between said characters such that a first given character may be less than, equal to, or greater than a second given character and wherein said processing means further comprises:
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compare state means for specifying three states, greater than, less than, and equal, for said storage section including means responsive to a compare reset control signal comprising one of said control signals for causing said compare state means to specify the equal state for said storage section; ordered comparing means for comparing said specification character to said selected character, for causing said said compare state means to specify the greater than state for said storage section if said storage section was in the equal state and said selected character was greater than said character of said specification word, and for causing said compare state means to specify the less than state for said storage section if said storage section was in the equal state and said selected character was less than said character of said specification word, said ordered comparing means being responsive to a numerical compare control signal comprising one of said control signals; means for causing said flag means to specify the inactive state for said storage section if said compare state means specifies the greater than state for said storage section, said means being responsive to a reset if greater than control signal comprising one of said control signals; means for causing said flag means to specify the inactive state for said storage section if said compare state means specifies the less than state for said storage section, said means being responsive to a reset if less than control signal comprising one of said control signals; and means for causing said flag means to specify the inactive state for said storage section if said compare state means specifies the equal state for said storage section, said means being responsive to a reset if equal control signal comprising one of said control signals. - View Dependent Claims (45)
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46. The content addressable memory of 44 wherein said ordered comparing means comprises means for comparing the numerical representation of said specification character to the numerical representation of said selected character.
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47. The content addressable memory of 15 wherein each said storage section further comprising:
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distance means for storing a number; means for storing a predetermined number in said distance means operative in response to a distance register reset signal comprising one of said control signals; means for computing a function value depending on said selected character and said specification character and for adding the said function value to the number stored in said distance mean operative in response to a distance calculating signal comprising one of said control signals; and reset means for causing said flag means to specify the inactive state for said storage section if the number stored in said distance means has a specified numerical relationship to a number comprising a specification character communicated on said control bus, said reset means being responsive to a distance compare signal comprising one of said control signals. - View Dependent Claims (48, 49, 50, 51, 52, 53)
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Specification