Method of updating layout of circuit element

• US 4,805,113 A
• Filed: 04/09/1986
• Issued: 02/14/1989
• Est. Priority Date: 04/10/1985
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Iwanabe, Makiko, Ishii, Tatsuki
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US06/849,831
• Time in Patent Office: 1,042 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/300, 364/521
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

For the purpose of satisfying placement constraint prescribed by design rule data, a region to which a plurality of circuit elements appertain is displayed in such a way that this region is moved to such a position as to environ a part of the circuit elements and at the same time is superposed on a layout graph thereof. The placement of the circuit elements is updated such that some elements placed outside the foregoing region among all the circuit elements are made to enter this region.

Claims

1. A method of updating a layout of circuit elements, comprising the steps of:

displaying a graph showing a placement state of respective circuit elements on the basis of placement data determined with a view to satisfying design rule data which includes a placement constraint for a plurality of circuit elements;

detecting data representing a group of circuit elements which infringe said placement constraint prescribed by said design rule data within the layout on the basis of said placement data;

detecting data corresponding to a region to which said group of circuit elements will have to appertain for the purpose of meeting said placement constraint;

displaying said region in such a manner that said region is so disposed as to encompass a part of the circuit elements in said group of circuit elements and to be superposed on said graph; and

modifying said placement data on the basis of an element layout modifying indication given from an operator who observes said graph displayed and said region displayed in superposition on said graph, and moves the placement of at least one circuit element of the circuit elements in said group of circuit elements into said region.

2. A method of updating a layout of circuit elements as set forth in claim 1, wherein the central position of said displayed region is moved to a position prescribed by the operator, thereby displaying said region.

3. A method of updating a layout of circuit elements as set forth in claim 1, wherein said circuit elements are disposed on an integrated circuit.

4. A method of updating a layout of circuit elements as set forth in claim 1, wherein said region is displayed as a rhombus.

5. A method of updating a layout of circuit elements as set forth in claim 4, wherein said circuit elements are disposed on an integrated circuit.

6. A method of updating a layout of circuit elements as set forth in claim 4, wherein the central position of said displayed region is moved to a position prescribed by the operator, thereby displaying said region.

7. A method of updating a layout of circuit elements as set forth in claim 4, wherein said lateral and perpendicular diagonal lengths of said rhombus are established according to an allowable value of electrostatic capacitance incident to the wiring between said respective elements, said allowable value being previously set as said placement constraint.

8. A method of updating a layout of circuit elements as set forth in claim 7, wherein said circuit elements are disposed on an integrated circuit.

9. A method of updating a layout of circuit elements as set forth in claim 4, wherein lateral and perpendicular diagonal lengths of said rhombus are determined according to allowable wiring lengths linking said respective elements, said allowable wiring lengths being preliminarily given as said placement constraint.

10. A method of updating a layout of circuit elements as set forth in claim 9, wherein said circuit elements are disposed on an integrated circuit.

11. A method of updating a layout of circuit elements as set forth in claim 9, wherein said lateral and perpendicular diagonal lengths of said rhombus are determined in such a way that they are independent from each other.

12. A method of updating a layout of circuit elements as set forth in claim 11, wherein said circuit elements are disposed on an integrated circuit.