Method for fabricating multilayer circuits

• US 4,806,188 A
• Filed: 03/04/1988
• Issued: 02/21/1989
• Est. Priority Date: 03/04/1988
• Status: Expired due to Fees

• Current Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Inventors: Rellick, Joseph R.
• Primary Examiner(s): Weston, Caleb
• Application Number:
  US07/164,452
• Time in Patent Office: 354 Days
• Field of Search: 156/89, 156/253, 29/851, 29/852, 264/58, 264/61, 264/67, 174/68.5
• US Class Current: 156/89.16
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/092 Dispersed materials, e.g. conductive pastes or inks
• CPC Class Codes: H05K 2203/068 Features of the lamination press or of the lamination process, e.g. using special separator sheets
• CPC Class Codes: H05K 2203/107 Using laser light shaping a substrate by laser ablation H05K3/0026
• CPC Class Codes: H05K 3/0017 Etching of the substrate by chemical or physical means
• CPC Class Codes: H05K 3/4667 characterized by using an inorganic intermediate insulating layer
• CPC Class Codes: Y10T 156/1057 Subsequent to assembly of laminae
• CPC Class Codes: Y10T 29/49163 with sintering of base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

The invention is directed to a method for fabricating multilayer circuits on rigid substrates using conventional dielectric green tape and thick film conductive pastes while maintaining excellent X-Y dimensional stability.

Claims

1. A method for the fabrication of multilayer circuits comprising the sequential steps of:

(a) providing a dimensionally stable electrically insulative substrate;

(b) applying to the substrate a patterned conductive layer;

(c) firing the patterned conductive layer;

(d) laminating to the fired patterned conductive layer and exposed areas of the substrate a layer of dielectric green tape;

(e) forming vias in selected positions through the layer of dielectric green tape in registration with the fired patterned conductive layer of step (c);

(f) firing the laminated dielectric green tape layer;

(g) filling the vias in the dielectric tape layer with a conductive metallization;

(h) firing the filled vias in the dielectric tape layer;

(i) applying a patterned conductive layer to the dielectric tape layer in registry with the vias therein;

(j) firing the patterned conductive layer; and

(k) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (d) through (j) until the desired number of circuit layers has been obtained.

2. The method of claim 1 in which step (f) is omitted and the laminated dielectric green tape layer and the via fill metallizations are co-fired in step (h).

3. The method of claim 1 in which steps (f) and (h) are eliminated and the dielectric green tape layer, via fill metallizations and overlying patterned conductive layer are co-fired in step (j).

4. The method of claim 1 in which step (h) is omitted and the via fill metallizations and overlying patterned conductive layer are co-fired in step (j).

5. A method for the fabrication of multilayer circuits comprising the sequential steps of:

(a) providing a dimensionally stable substrate;

(b) laminating to a surface of the substrate a layer of dielectric green tape;

(c) optionally forming vias in the laminated green tape;

(d) firing the laminated dielectric green tape layer;

(e) filling any vias in the laminated dielectric tape with a conductive metallization;

(f) firing any filled vias in the dielectric tape layer;

(g) applying to the dielectric tape layer a patterned conductive layer;

(h) firing the patterned conductive layer;

(i) laminating a dielectric green tape layer to the fired patterned conductive layer and exposed areas of the underlying dielectric tape layer;

(j) forming vias in the laminated green tape layer of step (i);

(k) firing the laminated green tape layer which was applied in step (j);

(l) filling the vias in the dielectric tape layer with a conductive metallization;

(m) firing the filled vias contained in the dielectric tape layer from step (1);

(n) applying to the dielectric tape layer a patterned conductive layer;

(o) firing the patterned conductive layer from step (n); and

(p) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (i) through (o) until the desired number of circuit layers has been obtained.

6. The method of claim 5 in which steps (f) and (m) are omitted and the via fill metallizations and patterned conductive layers are co-fired in steps (h) and (o), respectively.

7. The method of claim 5 in which steps (d) and (k) are omitted and the laminated green tape layers and via fill metallizations are co-fired in steps (f) and (m), respectively.

8. The method of claim 5 in which steps (d), (f), (k) and (m) are omitted and the laminated green tape layers, via fill metallizations and patterned conductive layers are co-fired in steps (h) and (o), respectively.