Method of manufacturing integrated circuit semiconductor device

• US 4,806,457 A
• Filed: 04/09/1987
• Issued: 02/21/1989
• Est. Priority Date: 04/10/1986
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yanagisawa, Masayuki
• Primary Examiner(s): Dees, Jose G.
• Application Number:
  US07/036,076
• Time in Patent Office: 684 Days
• Field of Search: 430/311, 430/30, 430/494, 437/229, 356/384
• US Class Current: 430/311
• CPC Class Codes: G03F 7/20 Exposure; Apparatus therefor photographic printing apparatus for making copies G03B27/00
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing integrated circuit semiconductor device in which a check pattern of resist film is formed for monitoring a state of an element-forming resist pattern having a narrow interval of 1.0 μm or less is disclosed. The check pattern is designed such that a plurality of resist stripes are arranged with intervals therebetween. Each of the intervals is of 1.0 μm or less and the width of the resist stripe is three times or more the interval.

Claims

1. A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that at least three resist stripes are arranged in parallel with interposing intervals, said intervals having different widths of 1μ

m or less, and each of said resist stripes having a width of three times or more the maximum width of said intervals and a length of ten times or more the maximum width of said intervals.

2. A method of claim 1, in which said resist stripes are four or more in number and widths of the intervals therebetween are successively reduced.

3. A method of claim 1, in which all of said resist stripes have the same width and the same length.

4. A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that a pair of resist stripes extend with interposing a narrow interval therebetween, said interval being divided at least three sections having different widths of 1μ

m or less, and each of said stripes having a width of three times or more the maximum width of said sections of said interval

5. A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that first and second resist stripes extend in parallel with interposing an interval having a constant width of 1 μ

m or less each of said first and second resist stripes being constituted by a plurality of portions each having different width, the width of one group of said portions being three times or more said constant width of said interval and the width of the other group of said portions being less than three times said constant width of said interval.

6. A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that a plurality of resist stripes having different widths are arranged with interposing intervals having a constant width of 1 μ

m or less, and the minimum width of said stripes being less than three times said constant width of said interval and the maximum width of said stripes being not less than three times said constant width of said interval.