Sample-and-hold circuit

• US 4,806,790 A
• Filed: 02/12/1988
• Issued: 02/21/1989
• Est. Priority Date: 02/16/1987
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sone, Kazuya
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US07/155,251
• Time in Patent Office: 375 Days
• Field of Search: 307/352, 307/353, 307/549, 307/551, 307/561, 307/565, 328/151
• US Class Current: 327/94
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

For elimination of a driftage of voltage at an output node, there is proposed a sampling-and-hold circuit comprising an n-p-n type charging transistor capable of charging up a hold-capacitor to a certain voltage level in proportion to the voltage level of an input signal, an n-p-n type driving transistor driven by the hold-capacitor for producing an output signal at a signal output node, and a clamping circuit operative to keep the voltage level of the base node of the charging transistor in a predetermined value is so far as the hold-capacitor keeps the certain voltage level, so that the hold-capacitor supplies a base current only to the driving transistor, thereby decreasing the driftage of voltage at the output node.

Claims

1. A sample-and-hold circuit having a sample mode and a hold mode, comprising:

(a) first and second voltage lines capable of supplying voltage levels different from each other;

(b) a signal input node where an input signal is supplied in said sample mode;

(c) a signal output node where an output signal is supplied;

(d) first, second and third nodes;

(e) a first transistor having a control node coupled to said signal input node and capable of providing a conduction path between said first voltage line and said first node in said sample mode;

(f) a series combination of a first constant current source and a level shifting circuit coupled between said first voltage line and said first node, said second node being provided between said first constant current source and said level shifting circuit;

(g) a second transistor having a control node coupled to said second node and a capable of providing a conduction path between said first voltage line and said third node;

(h) a hold-capacitor having two electrtodes one of which is coupled to said third node and the other of which is coupled to a constant voltage source, said hold-capacitor being charged up to a certain voltage level in proportion to a voltage level of said input signal for producing said output signal;

(i) second and third constant current sources each having an output node coupled to said second voltage line;

(j) a first switching circuit responsive to a control signal and capable of providing a conductive path between said first node and said second constant current source in said sample mode, said first switching circuit being capable of providing a conduction path between said second node and said second constant current source in said hold mode;

(k) a second switching circuit responsive to said control signal and capable of providing a conduction path between said third node and said third constant current source, said second switching circuit being capable of providing a conduction path between said first voltage line and said third constant current source; and

(l) voltage clamping means operative to cause said second node to have a predetermined voltage level at which said second transistor blocks said conduction path between said first voltage line and said third node in so far as said hold-capacitor keeps said certain voltage level.

2. A sample-and-hold circuit as set forth in claim 1, in which said sample-and-hold circuit further comprises a third transistor having a control node coupled to said third node and capable of providing a conduction path between said first voltage line and said signal output node, and a load current source coupled between said signal output node and said second voltage line.

3. A sample-and-hold circuit as set forth in claim 2, in which said voltage clamping means comprise a diode and a constant voltage source.

4. A sample-and-hold circuit as set forth in claim 3, in which said diode is formed by a fourth transistor having a control node coupled to one end of a conduction path formed therein.

5. A sample-and-hold circuit as set forth in claim 4, in which said first, second, third and fourth transistors are formed by n-p-n type bipolar transistors, respectively.

6. A sample-and-hold circuit as set forth in claim 2, in which said voltage clamping means comprise a diode coupled between said first node and said second node.

7. A sample-and-hold circuit as set forth in claim 6, in which said diode is formed by a fourth transistor having a control node coupled to one end of a conduction path formed therein.

8. A sample-and-hold circuit as set forth in claim 7, in which said first, second, third and fourth transistors are formed by n-p-n type bipolar transistors, respectively.

9. A sample-and-hold circuit as set forth in claim 5, in which said level shifting circuit comprises a series of diodes.

10. A sample-and-hold circuit as set forth in claim 9, in which each of said series of diode is formed by an n-p-n type bipolar transistor having a base node coupled to a collector node thereof.

11. A sample-and-hold circuit as set forth in claim 10, in which said first switching circuit comprises two n-p-n type bipolar transistors alternatively shifting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said first node and said second constant current source, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said second node and said second constant current source.

12. A sample-and-hold circuit as set forth in claim 11, in which said second switching circuit comprises two n-p-n type bipolar transistor alternatively shifting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said third node and said third constant current course, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said first voltage line and said third constant current source.

13. A sample-and-hold circuit as set forth in claim 12, in which all of said n-p-n type bipolar transistors have respective forwardly biassing voltage approximately equal to one another.

14. A sample-and-hold circuit as set forth in claim 8, in which said level shifting circuit comprises a series of diodes.

15. A sample-and-hold circuit as set forth in claim 14, in which each of said series of diode is formed by an n-p-n type bipolar transistor having a base node coupled to a collector node thereof.

16. A sample-and-hold circuit as set forth in claim 15, in which said first switching circuit comprises two n-p-n type bipolar transistors alternatively shifting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said first node and said second constant current source, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said second node and said second constant current source.

17. A sample-and-hold circuit as set forth in claim 16, in which said second switching circuit comprises two n-p-n type bipolar transistors alternatively shfiting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said third node and said third constant current source, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said first voltage line and said third constant current source.

18. A sample-and-hold circuit as set forth in claim 17, in which all of said n-p-n type bipolar transistors have respective forwardly biassing voltage approximately equal to one another.