Active load for emitter coupled logic gate

• US 4,806,796 A
• Filed: 03/28/1988
• Issued: 02/21/1989
• Est. Priority Date: 03/28/1988
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bushey, Thomas P., Hwang, Bor-Yuan
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Thai, Nancy
• Application Number:
  US07/174,269
• Time in Patent Office: 330 Days
• Field of Search: 307/455, 307/358, 307/362, 307/363, 307/355, 307/290, 307/291, 307/456, 307/454, 307/443
• US Class Current: 326/126
• CPC Class Codes: H03K 19/013 in bipolar transistor circuits
• CPC Class Codes: H03K 19/086 Emitter coupled logic

Abstract

An active load for a CML or ECL logic gate for substantially increasing the speed of the gate comprises a transistor having its base coupled to its collector by a first resistor, and its collector-emitter path coupled in series with a second resistor. This load provides an inductive impedance when the small signal emitter resistance is less than the sum of the resistance of the base and the first resistor, causing a peaking effect resulting in high switching speed.

Claims

1. An improved logic gate having first and second voltage terminals, first and second input terminals, a first output terminal, a first current source, a first transistor having a base coupled to said first input terminal, an emitter coupled to said first voltage terminal by said first current source, and a collector coupled to said first output terminal, and a second transistor having a base coupled to said second input terminal, an emitter coupled to said first voltage terminal by said first current source, and having a collector, said improvement comprising:

a first resistor;

a second resistor;

a third resistor;

a fourth resistor;

a third transistor having its base coupled to its collector by said first resistor, and its collector-emitter path coupled in series with said second resistor between said collector of said first transistor and said second voltage terminal; and

a fourth transistor having its base coupled to its collector by said third resistor, and its collector-emitter path coupled in series with said fourth resistor between said collector of said second transistor and said second voltage terminal.

2. The improved logic gate according to claim 1 further comprising:

a second output terminal;

first means coupled between said collector of said first transistor and said first output terminal for amplifying the voltage on said collector of said first transistor; and

second means coupled between said collector of said second transistor and said second output terminal for amplifying the voltage on said collector of said second transistor.

3. The improved logic gate according to claim 1 further comprising:

a second output terminal;

a second current source;

a third current source;

a fifth transistor coupled between said collector of said first transistor and said first output terminal having a collector coupled to said second voltage terminal, a base coupled to the collector of said first transistor, and an emitter coupled to said first output terminal and coupled to said first voltage terminal by said second current source; and

a sixth transistor having a collector coupled to said second voltage terminal, a base coupled to the collector of said second transistor, and an emitter coupled to said second output terminal and coupled to said first voltage terminal by said third current source.

11. The improved logic gate according to claim 1 wherein the small signal emitter resistance of said third transistor is less in magnitude than the sum of the resistances of said first resistor and the base of said third transistor and the small signal emitter resistance of said fourth transistor is less in magnitude than the sum of the resistances of said second resistor and the base of said fourth transistor.

4. A logic gate comprising:

a first supply voltage terminal;

a second supply voltage terminal;

a first input terminal;

a second input terminal;

a first output terminal;

a first current source;

a first resistor;

a second resistor;

a third resistor;

a fourth resistor;

a first transistor having a base coupled to said first input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector to said first output terminal;

a second transistor having a base coupled to said second input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector;

a third transistor having its base coupled to its collector by said first resistor, and its collector-emitter current path coupled in series with said second resistor between said collector of said first transistor and said first supply voltage terminal; and

a fourth transistor having its base coupled to its collector by said third resistor, and its collector-emitter current path coupled in series with said fourth resistor between said collector of said second transistor and said first supply voltage terminal.

5. The logic gate according to claim 4 further comprising:

a second output terminal;

first means coupled between said collector of said first transistor and said first output terminal for amplifying the voltage on said collector of said first transistor; and

second means coupled between said collector of said second transistor and said second output terminal for amplifying the voltage on said collector of said second transistor.

6. The improved logic gate according to claim 4 further comprising:

a second output terminal;

a second current source;

a third current source;

a fifth transistor having a collector coupled to said second voltage terminal, a base coupled to the collector of said first transistor, and an emitter coupled to said first output terminal and coupled to said first voltage terminal by said second current source; and

a sixth transistor having a collector coupled to said second voltage terminal, a base coupled to the collector of said second transistor, and an emitter coupled to said second output terminal and coupled to said first voltage terminal by said third current source.

7. An logic gate comprising:

a first supply voltage terminal;

a second supply voltage terminal;

a first input terminal;

a second input terminal;

a first output terminal;

a first current source;

a first resistor;

a second resistor;

a first transistor having a base coupled to said first input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector;

a second transistor having a base coupled to said second input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector;

a third transistor having its base coupled to its collector by said first resistor, and its collector-emitter current path coupled in series with said second resistor between said collector of said first transistor and said second supply voltage terminal; and

first means coupled between said collector of said first transistor and said first output terminal for amplifying the voltage on said collector of said first transistor.

8. The logic gate according to claim 7 wherein said first means comprises:

a second current source; and

a fourth transistor having a collector coupled to said second voltage terminal, a base coupled to the collector of said first transistor, and an emitter coupled to said first output terminal and coupled to said first voltage terminal by said second current source.

9. The logic gate according to claim 7 further comprising:

a second output terminal;

a third resistor;

a fourth resistor; and

a fourth transistor having its base coupled to its collector by said third resistor, and its collector-emitter current path coupled in series with said fourth resistor between said collector of said second transistor and said second supply voltage terminal; and

second means coupled between said collector of said second transistor and said second output terminal for amplifying the voltage on said collector of said second transistor.

10. The logic gate according to claim 9 wherein said second means comprises:

a third current source; and

a sixth transistor having a collector coupled to said second voltage terminal, a base coupled to the collector of said second transistor, and an emitter coupled to said second output terminal and coupled to said first voltage terminal by said third current source.