Method and apparatus for multiplexing television signals

• US 4,807,030 A
• Filed: 06/13/1986
• Issued: 02/21/1989
• Est. Priority Date: 12/13/1985
• Status: Expired due to Fees

• Current Assignee: Internal Revenue Service United States Treasury Department, Multilink Inc.
• Original Assignee: Multilink Inc.
• Inventors: Sacks, Jack
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US06/874,042
• Time in Patent Office: 984 Days
• Field of Search: 358/142, 358/146, 358/133, 358/136, 358/11, 358/12, 358/141
• US Class Current: 375/240.25
• CPC Class Codes: H04N 7/0806 the signals being two or more video signals H04N7/0803, H04N7/081 take precedence
• CPC Class Codes: H04N 7/122 involving expansion and subsequent compression of a signal segment, e.g. a frame, a line

Abstract

A decoder for use in a multiplexing system wherein the adjacent frame lines of a first program are summed and differenced, and the sum signal and time-compressed difference signal of each line pair is transmitted during the period allotted for transmission of a single line, thereby transmitting data for two lines in the time allotted for a single line. The decoder avoids a need for complex digital wall filters at the input by sampling the timed-compressed difference signals at a non-unity multiple of the rate used for sampling the sum signals. The multiple is sufficiently fast to enable the standard "front-end" low pass filter of the decoder to function as an interpolation filter, eliminating the artifacts which would otherwise require the use of the complex filter. The disclosed decoder additionally includes a first memory-sharing arrangement wherein memory addresses are accessed during each operating cycle in a manner which permits data to be written into memory prior to the complete reading out of data from the previous operating cycle. A second memory-sharing arrangement is included wherein memory addresses are accessed during each operating cycle in a manner which permits data to be read out of the memory prior to the complete writing of data for that operating cycle, enabling re-use of certain memory addresses during the operating cycle.

Claims

1. A decoder for separating an encoded television frame representing odd and even field lines of an unencoded television frame, the decoder comprising:

(a) means for receiving an input signal containing the encoded television frame comprising a plurality of sum and difference signal pairs,

wherein each of said signal pairs comprises a sum signal indicative of the sum of respective pair of field lines of the unencoded television frame,

and a time-compressed difference signal indicative of the time-compressed bandlimited difference between a respective pair of field lines of the unencoded television frame;

(b) first means for sampling and holding the sum signals of the signal pairs at a first effective rate;

(c) second means for effectively sampling and holding the time-compressed difference signals of the signal pairs at a second effective rate which is a non-unity multiple of said first effective rate to produce respective time-expanded difference signals;

(d) means for adding the sampled and held sum signals to the time-expanded difference signals to substantially recover one of the paired field lines of each of the field line pairs; and

(e) means for differencing the sampled and held sum signals and the time-expanded difference signals to substantially recover the other of the field lines of each of the field line pairs.

2. The decoder of claim 1 including memory means for storing the samples and held time-expanded difference signals in uniquely addressable memory locations, and

means for applying the sum signal and the stored time-expanded difference signal in a time-aligned manner to the adding means the differencing means as the sum signal is sampled by the first sample and hold means.

3. The decoder of claim 1 wherein the first and second effective rates are multiples of the chroma subcarrier frequency.

4. The decoder of claim 3 including oscillator means responsive to a signal at the chroma subcarrier frequency of a television signal to produce timing signals at respective harmonics of the chroma subcarrier frequency, and

switch means for periodically phase-locking the oscillator means to the input signal.

7. The decoder of claim 1 or claim 5 wherein said means for sampling and holding the time-compressed difference signals includes n independently clocked sample and hold devices, where n is an integer greater than 1;

means for simultaneously applying each of the time-compressed difference signals to the n sample and hold devices; and

means for clocking each of the sample and hold devices at said first effective rate, but at mutually offset times, to effectively sample and hold the time-compressed difference signals at a multiple of said first effective rate.

8. The decoder of claim 7 wherein the first sample and hold means includes means for sampling the sum signals at the first effective rate and applying the sampled sum signals to the adding and differencing means, and including

means for clocking the sample and hold devices at 1/n of the first effective rate of simultaneous application of the sum and difference signals to the adding means and differencing means.

9. The decoder of claim 1 or 5 wherein said means for sampling and holding the time-compressed difference signals includes n independently clocked analog storage devices, where n is an integer greater than 1;

means for applying the time-compressed difference signals in parallel to the n storage devices; and

means for clocking each of the n analog storage devices at said first effective rate, but at mutually offset times, to effectively sample and hold the difference signals value at a multiple of the first effective rate.

10. The decoder of claim 9 including

means for clocking the storage devices containing the held difference signals at 1/n of the first effective rate for simultaneous application of the sum and difference signals to the adding means and differencing means.

11. The decoder of claim 1 wherein said means for sampling and holding the time-compressed difference signals includes a plurality of clocked sample and hold devices;

means for delaying the timed-compressed difference signals so that the time-compressed difference signals are applied to at least some of the devices by unique delay intervals; and

means for clocking each of the sample and hold devices at said first effective rate to sample the delayed time-compressed difference signals,

the sum of the delay intervals being no greater than the interval between clockings of each device,

whereby values of the time-compressed difference signals which occur between clockings of one of the devices are delayed and are sample at the first effective rate by other of the devices so as to effectively sample the time-compressed difference signals at a sample which is the multiple of the first effective rate.

5. A decoder for separating an encoded television frame representing odd and even field lines of an unencoded television frame, the decoder comprising:

(a) means for receiving an input signal containing the encoded television frame comprising a plurality of sum and difference signal pairs,

wherein each of said signal pairs comprises a sum signal indicative of the sum of a respective pair of field lines of the unencoded television frame, and a time compressed bandlimited difference signal indicative of the time-compressed bandlimited difference between a respective pair of field lines of the unencoded television frame;

(b) first means for sampling and holding the sum signals of the signal pairs at a first effective rate;

(c) second means for effectively sampling and holding the time-compressed difference signals of the respective signal pairs at a second effective rate which is a multiple of said first effective rate to produce respective time-expanded difference signals,

said multiple being proportional to the compression ratio of the difference signals to the sum signals;

(d) memory means for storing the sampled and held values of the time-expanded difference signals in uniquely addressable memory locations,

(e) means for adding the sampled and held sum signals to the time-expanded difference signals for each field line pair to substantially recover one field lines of each pair;

(f) means for differencing the sampled and held sum signals and time-expanded difference signals for each field line pair to substantially recover the other of the field lines of each pair; and

(g) means for applying the sampled and held sum signals and the stored time-expanded difference signals in a time-aligned manner to the adding means and the differencing means as the sum signals are sampled by the first sample and hold means.

6. The decoder of claim 5 wherein said means for sampling and holding the time-compressed difference signals includes a plurality of clocked sample and hold devices;

means for delaying the time-compressed difference signals so that the time-compressed difference signals are applied to at least some of the devices by unique delay intervals; and

means for clocking each of the sample and hold devices at said first effective rate to sample the delayed time-compressed difference signals, the sum of the delay intervals being no greater than the interval between clockings of each device.

whereby values of the time-compressed difference signals which occur between clockings of one of the device are delayed and are sample at the first effective rate by other of the devices so as to effectively sample the time-compressed difference signals at a sample rate which is the multiple of the first effective rate.

12. The decoder of claim 9 or claim 6 wherein the devices have offset voltages and gain characteristics which generate inequalities between a sampled input signal and the outputted held signal, and the respective offset voltage and gain characteristics of the devices are unrelated, the decoder including means for averaging each difference signal output from at least one of the device with the sequentially adjacent values from at least some of the other devices to substantially remove the harmonic component induced by any respective unrelated offset voltage or gain characteristic of the devices.

13. A decoder for separating an encoded television frame representing odd and even field lines of an unencoded television frame, the decoder comprising:

(a) means for receiving an input signal containing the encoded television frame comprising a plurality of sum and difference signal pairs,

wherein each of said signal pairs comprises a sum signal indicative of the sum of a respective pair of field lines of the unencoded television frame,

and a time-compressed difference signal indicative of the time-compressed difference between the a respective pair of field lines of the unencoded television frame;

(b) means for effectively sampling and holding the sum signals of the signals pairs at a first effective rate;

(c) means for effectively sampling and holding the time-compressed difference signals of the signal pairs at a second effective rate which is a multiple of said first effective rate to produce respective time-expanded difference signals;

(d) means for time expanding the sampled and held difference signals to establish a number of samples substantially equal to the number of samples of the sampled and held sum signals;

(e) means for adding the sampled and held sum signals to the time-expanded difference signals to substantially recover one of the paired field lines of each of the field line pairs;

(f) means for differencing the sampled and held sum signals and the time-expanded difference signals to substantially recover the other of the paired field lines of each of the field line pairs;

(g) first memory means having uniquely addressable locations for storing the recovered line signals for at least a portion of one of the fields;

(h) second memory means having uniquely addressable locations for storing the the recovered line signals of the other field; and

(i) means for accessing the first and second memory means to output the recovered line signals for the frame.

14. The decoder of claim 13 including means for simultaneously writing first field data into said first memory means and reading said data from said first memory means,

the writing being commenced before the reading,

a portion of the field data being written thereafter into memory locations from which the field data has been read.

15. A decoder for separating a pair of multiplexed television programs, each program comprising a plurality of encoded television frames which respectively represent odd and even field lines of an unencoded television frame, the decoder comprising:

(a) means for receiving an input signal containing a succession of the encoded television frames, each encoded frame comprising a plurality of sum and difference signal pairs,

wherein each of said signals pairs comprises a sum signal indicative of the sum of a respective pair of field lines of the respective unencoded television frame, and

a time-compressed difference signal indicative of the time-compressed difference between the respective pair of field lines in the respective unencoded television frame;

(b) means for effectively sampling and holding the sum signals of the signal pairs at a first effective rate;

(c) means for effectively sampling and holding the time-compressed difference signals of the signal pairs;

(d) means for time-expanding the sampled and held difference signals to re-establish their pre-compression time base;

(e) means for adding the sampled and held sum signals to the time-expanded difference signals to substantially recover one of the paired field lines of each of the field line pairs of the unencoded television frames;

(f) means for differencing the sampled and held sum signals and the time-expanded difference signals to substantially recover the the other of the paired field lines of each of the field line pairs of the unencoded television frames;

(g) first memory means having uniquely addressable locations for storing the recovered line signals for at least a portion of one of the fields;

(h) second memory means having uniquely addressable locations for storing the recovered line signals of other of the fields; and

(i) means for accessing the first and second memory means to output the recovered line signals to produce recovered unencoded frames.

16. The decoder of claim 15 including means for writing first field data into said first memory means and reading said first data from said first memory means,

the writing being commenced before the reading,

wherein a portion of the first field data is written into memory locations from which a portion of the first field data has been read.

17. The decoder of claim 15 including means for writing second field data of one of said programs into said second memory means and reading second field data from the other of said programs out of said second memory means,

the reading being commenced before the writing,

such that data from said one program is written into memory locations from which the data from said other program has been read.

18. In a video multiplexing system wherein data for each of a plurality of video frames, each comprising a first field and second field is received within a field interval during each of succession of operating cycles, and wherein each field of each frame is to be produced within a field interval during a respective one of said cycles, a method for buffering the data comprising the steps of:

(a) sizing a first memory to store at least a portion of the data from one of the fields;

(b) sizing a second memory to store substantially all the data from one of the fields;

(c) structuring the first and second memories so that each may be simultaneously written into and read from; and

(d) within each said operating cycles,

(1) writing the data for the first field of an incoming frame into successively addressed locations of the first memory;

(2) reading the written data for the first field from the successively addressed locations of the first memory during a field interval, the writing of the data being commenced prior to the start of the reading of the data;

(3) reading previous data which was written for a second field during the previous operating cycle from successively addressed locations of the second memory; and

(4) writing the data for the second field of the incoming frame in the successively addressed locations of the second memory from which the previous data has been read.

19. The method of claim 18 including the step of arranging the incoming data in each memory among a plurality of chips so that no chip must be simultaneously read from and written into during the operating cycle.

20. The method of claim 19 further including the steps of;

cyclically addressing a plurality of the chips of the first memory during a respective portion of each operating cycle;

writing data for at least one of a plurality of successive field lines into each chip of the first memory during each addressing cycle;

wherein the number of the field line stored during ones of the addressing cycles is smaller than the number stored during previous addressing cycles of the respective portion.

21. The method of claim 19 further including the steps of;

cyclically addressing a plurality of the chips of the second memory during a respective portion of each operating cycle;

writing data for at least one of a plurality of successive field lines into each chip of the second memory during each addressing cycle;

wherein the number of field lines stored during ones of the addressing cycles is larger that the number stored during previous addressing cycles of the portion.

22. The method of claim 19 including the step of writing the data into the first memory as illustrated in FIG. 14.

23. The method if claim 19 including the step of writing the data into the second memory as illustrated in FIG. 13.