Noise reduction circuit for video signal having field memory

• US 4,807,034 A
• Filed: 03/03/1988
• Issued: 02/21/1989
• Est. Priority Date: 03/12/1987
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kisou, Masaaki, Takeuchi, Motohiko
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Peng, John K.
• Application Number:
  US07/163,605
• Time in Patent Office: 355 Days
• Field of Search: 358/105, 358/166, 358/167, 358/36, 358/340, 358/336
• US Class Current: 348/620
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
• CPC Class Codes: H04N 5/911 for the suppression of noise H04N5/932 takes precedence

Abstract

A noise reduction circuit allows a field memory to store 1-field data of a video signal through a subtracting circuit. The video signal is supplied from a VTR through an A/D converter. The noise reduction circuit causes a subtracting circuit to subtract a delayed video signal, which is supplied from the field memory with a 1-field time delay, from the video signal and allows the resultant signal to be output as a field difference signal. A noise component included in the video signal is extracted by a noise extracting circuit in accordance with the field difference signal, and is output to the subtracting circuit. In a comparing circuit, the noise component is compared with a predetermined reference value so as to determine whether the video signal represents a motion or motionless picture. In accordance with this determination result, memory control circuit controls whether to write the video signal supplied from the subtracting circuit in the field memory. In addition, a video signal from which the noise component is removed is supplied from the subtracting circuit and monitored on a CRT display through a D/A converter or the like.

Claims

1. A noise reduction circuit for a video signal, said circuit comprising:

an A/D converter for converting an input video signal into a digital signal;

first subtracting circuit means for reducing a noise component included in said input video signal of said digital signal from said A/D converter by subtracting a noise component signal corresponding to said noise component from said digital signal;

field memory means for storing at least 1-field data of an output from said first subtracting circuit means and allowing said stored data to be read out with a predetermined delay time;

second subtracting circuit means for subtracting said data read out from said field memory means from said digital signal supplied from said A/D converter and outputting a subtraction result as a field difference signal;

noise extracting circuit means for selecting said noise component signal corresponding to said noise component in accordance with said field difference signal from said second subtracting circuit means and outputting said selected noise component signal to said first subtracting circuit means;

comparing circuit means for comparing said field difference signal from said second subtracting circuit means with a predetermined reference value, detecting said input video signal as a signal representing a motion picture when said field difference signal is larger than said reference value, and outputting a detection signal corresponding to said motion picture, and detecting said input video signal as a signal representing a motionless picture when said field difference signal is smaller than said reference value, and outputting a detection signal corresponding to said motionless picture;

memory control circuit means for controlling whether to write a video signal supplied from said first subtracting circuit means to said field memory means in accordance with said detection signal output from said comparing circuit means; and

a D/A converter for converting said digital signal from which said noise component is removed by said first subtracting circuit means into an analog signal and outputting a resultant signal.

2. A circuit according to claim 1, wherein said memory control circuit means inhibits the video signal subtracted by said first subtracting circuit means to be written in said field memory means when said input video is determined to represent a motionless picture by said comparing circuit means in one of field periods constituting a 1-frame period, writes said input signal subtracted by said first subtracting circuit means in said field memory means when said input video signal is determined to represent a motion picture, and writes said video signal subtracted by said first subtracting circuit in said field memory means regardless of a detection signal output from said comparing circuit means in the other of said field periods constituting said 1-frame period.

3. A circuit according to claim 2, wherein said memory control circuit means uses a switching pulse from a magnetic head as a signal for detecting one of said field periods constituting said 1-frame period.

4. A circuit according to claim 3, wherein said noise extracting circuit means comprises a ROM for selecting a noise component signal written in advance in accordance with said field difference signal from said second subtracting circuit means and outputting said selected signal to said first subtracting circuit means.

5. A circuit according to claim 4, wherein a characteristic of said noise component signal written in said noise extracting circuit means in advance is changed every field.

6. A circuit according to claim 5, wherein said predetermined reference value used by said comparing circuit means is set in accordance with a level of said field difference signal.

7. A circuit according to claim 6, wherein said first subtracting circuit means comprises an adder for adding said digital signal to said noise component, and said second subtracting circuit comprises an inverter for inverting data read out from said field memory, and an adder for adding data through said inverter to said digital signal.

8. A noise reduction circuit for a video signal, said circuit comprising:

an A/D converter for converting an input video signal into a digital signal;

first subtracting circuit means for reducing a noise component included in said input video signal of said digital signal from said A/D converter by subtracting a noise component signal corresponding to said noise component from said digital signal;

field memory means for storing at least 1-field data of an output from said first subtracting circuit means and allowing said stored data to be read out with a predetermined delay time;

second subtracting circuit means for subtracting said data read out from said field memory means from said digital signal supplied from said A/D converter and outputting a subtraction result as a field difference signal;

noise extracting circuit means for selecting said noise component signal corresponding to said noise component in accordance with said field difference signal from said second subtracting circuit means and outputting said selected noise component signal to said first subtracting circuit means;

delay circuit means for delaying said data read out from said field memory means for a predetermined period of time and outputting said data;

switching means, inserted between said first subtracting circuit means and said field memory means, for respectively supplying said video signal output from said first subtracting circuit means and a delayed video signal output from said delay circuit means to first and second terminals, and outputting either said video signal or said delayed video signal to said field memory means by switching and selecting said first or second terminal;

memory control circuit means for determining whether said input signal is regarded as a signal representing a motion or motionless picture in accordance with said field difference signal output from said noise extracting circuit means and switching said outputs supplied to said switching means by switching said terminals thereof, thereby controlling whether to write a video signal input to said field memory means; and

a D/A converter for converting said digital signal from which said noise component is removed by said first subtracting circuit means into an analog signal and outputting a resultant signal.

9. A circuit according to claim 8, wherein said memory control circuit means inhibits said video signal to be written in said field memory means by switching a switching terminal of said switching means to said second terminal when said input video represents a motionless picture in one of field periods constituting a 1-frame period, writes said input signal in said field memory means by switching said switching terminal of said switching means to said first terminal when said input video signal represents a motion picture, and writes said video signal in said field memory means by switching said switching terminal of said switching means to said first terminal regardless of whether said input video signal represents a motion or motionless picture in the other of said field periods constituting said 1-frame period.

10. A circuit according to claim 9, wherein said memory control circuit means uses a switching pulse from a magnetic head as a signal for detecting one of said field periods constituting said 1-frame period.

11. A circuit according to claim 10, wherein said noise extracting circuit means comprises a ROM for selecting a noise component signal written in advance in accordance with said field difference signal from said second subtracting circuit means and outputting said selected signal to said first subtracting circuit means.

12. A circuit according to claim 11, wherein a characteristic of said noise component signal written in said noise extracting circuit means in advance is changed every field.

13. A circuit according to claim 12, wherein said first subtracting circuit means comprises an adder for adding said digital signal to said noise component, and said second subtracting circuit comprises an inverter for inverting data read out from said field memory, and an adder for adding data through said inverter to said digital signal.