Voltage multiplying and inverting charge pump

• US 4,807,104 A
• Filed: 04/15/1988
• Issued: 02/21/1989
• Est. Priority Date: 04/15/1988
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Floyd, Michael D., Stump, Jeffrey D.
• Primary Examiner(s): Salce, Patrick R.
• Assistant Examiner(s): Sterrett, Jeffrey
• Application Number:
  US07/182,010
• Time in Patent Office: 312 Days
• Field of Search: 307/110, 363/59, 363/60, 363/63
• US Class Current: 363/59
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A charge pump circuit and associated method is provided for outputting either a positive or a negative output voltage, or both, which each may have a predetermined magnitude which is an integer multiple of the magnitude of a power supply voltage used to power the circuit. In one form, a first capacitor is charged to the power supply voltage. The first capacitor is coupled to the power supply voltage to develop a double voltage transfer supply with the supply voltage. Second and third capacitors are charged by the double voltage transfer supply. The second capacitor is used to store the charge from the first capacitor for a continuous output voltage having a magnitude which is twice the magnitude of the power supply. The third capacitor may be reconfigured to generate a negative transfer voltage. The negative transfer voltage is used to charge a fourth capacitor which provides a negative output voltage with twice the magnitude of the power supply voltage.

Claims

1. A voltage doubling and inverting charge pump circuit, comprising:

a first switch having a first terminal coupled to a power supply terminal for receiving a power supply voltage, a second terminal, and a control terminal for receiving a first control signal;

a first capacitor having a first electrode coupled to the second terminal of the first switch, and having a second electrode;

a second switch having a first terminal coupled to the second electrode of the first capacitor, having a second terminal coupled to a reference voltage terminal, and having a control terminal for receiving the first control signal;

a third switch having a first terminal coupled to the first electrode of the first capacitor, a second terminal coupled to a first output terminal which provides an output voltage of a first polarity and substantially twice the power supply voltage, and a control terminal for receiving a second control signal;

a second capacitor having a first electrode coupled to the first output terminal, and having a second electrode coupled to the power supply terminal;

a fourth switch having a first terminal coupled to the power supply terminal, a second terminal coupled to the second electrode of the first capacitor, and a control terminal for receiving the second control terminal;

a fifth switch having a first terminal coupled to the first electrode of the first capacitor, a second terminal, and a control terminal for receiving the second control signal;

a third capacitor having a first electrode coupled to the second terminal of the fifth switch, and having a second electrode;

a sixth switch having a first terminal coupled to the second electrode of the third capacitor, a second terminal coupled to the reference voltage terminal, and a control terminal for receiving the second control signal;

a seventh switch having a first terminal coupled to the first electrode of the third capacitor, a second terminal coupled to the reference voltage terminal, and a control terminal for receiving the first control signal;

a fourth capacitor having a first electrode coupled to the second terminal of the seventh switch, and having a second electrode coupled to a second output terminal which provides an output voltage of a second polarity substantially twice the power supply voltage; and

an eighth switch having a first terminal coupled to the second output terminal, a second terminal coupled to the second electrode of the third capacitor, and a control terminal coupled to the first control signal.

2. The voltage doubling and inverting charge pump circuit of claim 1 wherein said first and second control signals are nonoverlapping clock signals.

3. The voltage doubling and inverting charge pump circuit of claim 1 wherein said first polarity is a positive polarity relative to a reference voltage coupled to the reference voltage terminal and said second polarity is a negative polarity relative to the reference voltage.

4. A method for providing a positive and a negative output voltage for a circuit, each output voltage having a magnitude substantially twice a magnitude of a power supply voltage for powering the circuit, comprising the steps of:

charging a first capacitor of the circuit to the power supply voltage by coupling a first electrode of the first capacitor to the power supply voltage and a second electrode of the first capacitor to a reference voltage terminal;

charging a second capacitor to the power supply voltage;

coupling the second electrode of the first capacitor to the power supply voltage;

coupling a third capacitor between the first electrode of the first capacitor and the reference voltage terminal to charge the third capacitor to substantially twice the power supply voltage;

outputting a first output voltage equal to a sum of voltage stored by the second capacitor and the power supply voltage;

coupling a fourth capacitor in parallel with the third capacitor to charge share charge from the third capacitor onto the fourth capacitor; and

outputting a second output voltage equal to voltage stored by the fourth capacitor.

5. In a voltage multiplying circuit, a method for providing an output voltage which is a predetermined integer mulitple of a magnitude of a power supply voltage which powers the circuit, comprising the steps of:

providing a first voltage transfer capacitor and charging the first voltage transfer capacitor to the power supply voltage;

selectively coupling a predetermined plurality of additional voltage transfer capacitors to the first voltage transfer capacitor and charging each additional voltage transfer capacitor to a voltage which is substantially twice the power supply voltage;

providing a single reservoir capacitor between a reference voltage terminal and an output terminal; and

selectively coupling each of the voltage transfer capacitors to the single reservoir capacitor at the output terminal to charge the reservoir capacitor to the predetermined integer multiple of the power supply voltage.