Interprocessor communication

• US 4,807,116 A
• Filed: 05/18/1987
• Issued: 02/21/1989
• Est. Priority Date: 09/07/1976
• Status: Expired due to Term

• Current Assignee: Tandem Computers Incorporated (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Green, Michael D., Wierenga, Steven W., Bartlett, Joel F., Mackie, David R., McEvoy, Dennis L., Katzman, James A., Treybig, James G., Hayashi, Steven J., Bixler, Richard M., Despotakis, John A., Davidow, William H., Greig, David A., Graziano, Peter J.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US07/052,095
• Time in Patent Office: 645 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/85
• US Class Current: 710/113
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 11/2023 Failover techniques
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 13/122 where hardware performs an I/O function other than control of data transfer
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/366 using a centralised polling arbiter
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: G06F 7/78 : for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor

Abstract

In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i.e., busy or available); and the bus controller then signaling transmission commencement.

Claims

1. A multiprocessor system comprising:

a plurality of separate processor modules, each of said plurality of separate processor modules being capable of conducting data processing operations, including transmitting information to or receiving information from any of said separate processor modules, a processor module transmitting information being identified as a sender processor module and a module receiving information being identified as a receiver processor module;

bus means coupling the plurality of separate processor modules to one another for enabling communication therebetween, the bus means including bus controller means operable to enable processor module to processor module communication on the bus means;

request means included in said sender processor module for generating a send request signal on said bus means when said sender processor module is ready to transmit;

polling means included in said bus controller means and responsive to said send request signal for sequentially polling said plurality of separate processor modules to identify said sender processor module by its place in the sequence;

identification means included in said sender processor module and responsive to said poll for generating an identify signal for identifying one of said plurality of separate processor modules as a receiver processor module;

interrogation means included in said bus controller means and responsive to said identify signal for interrogating through the bus means said receiver processor module to determine whether said receive processor module is ready to receive a transmission;

acknowledgment means in said receiver processor module responsive to said interrogating means for generating a ready signal to indicate that said receiver processor module is ready to receive a transmission; and

transmit means included in said bus controller means and responsive to said ready signal for enabling said sender processor module to transmit to said receiver processor module.

2. The invention defined in claim 1, the bus controller means including select means for producing a select signal to establish the sender-receiver pair of processor modules and to exclude other processor modules from transmitting on the bus simultaneously with the selected sender processor module.

3. A method by which a first one of a plurality of processor modules may communicate by means of an interprocessor bus and bus controller with any other of said plurality of processor modules involving the steps of:

a one of the processor modules generating a send request when ready to transmit;

the bus controller sequentially polling each of said plurality of processor modules in response to said send request to locate the one processor module by its place in the sequence which is ready to transmit;

identifying another of said processor modules as a receiver processor module from information provided by the one processor module in response to the polling step;

the bus controller interrogating the receiver processor module to determine whether the receiver processor module is ready to receive; and

the bus controller enabling the sender processor module to transmit to the receiver processor module when said receiver processor module is ready to receive a transmission.

4. A method by which any one of a plurality of processor modules may communicate by means of an interprocessor bus and bus controller with any other of said plurality of processor modules involving the steps of:

a one of the processor modules generating a send request when ready to transmit;

said bus controller sequentially polling said plurality of processor modules in response to said send request to identify the one processor module by its place in the sequence;

identifying a second of said processor modules from information supplied by the one processor module in response to said polling step as a receiver processor module;

said bus controller asserting a select signal to establish the sender-receiver pair of processor modules, the other processor modules being prohibited from transmitting on the bus simultaneously with the selected sender processor module during existence of the select signal;

said bus controller interrogating the receiver processor module to determine whether the receiver processor module is ready to receive; and

said bus controller enabling the sender processor module to transmit to the receiver processor module when said receiver processor module is ready to receive a transmission.