Hybrid analog-digital associative neural network
First Claim
1. A hybrid analog-digital neural network comprisinga first random access memory for storing an N×
- N matrix of synaptic information in the form of binary 1 and 0 digits,an array of N analog amplifiers for performing the neuron function of said network, said array of amplifiers being numbered 1 through N corresponding to columns of said matrix,a first array of N electronic switches, each having an input terminal, an output terminal and a control terminal, one switch for each column having its control terminal connected to receive a binary signal of said synaptic information matrix stored in said first memory to enable current to flow through the switch from an input terminal to an output terminal thereof,a first summing amplifier having input and output terminals and a first array of N resistors, one resistor for each of said switches, connecting said switches to the input terminal of said summing amplifier,a first array of N sample-and-hold devices for sampling and holding an output signal at the output terminal of said summing amplifier in response to a control signal, said array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence,means for generating first and second timing signals where said first consists of N timing signals for every one of said second timing signals,means for producing and sequentially applying said control signal to said first array of N sample-and-hold devices in response to said first timing signal, said first array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence,a second array of N sample-and-hold devices having its input terminals connected to said array of analog amplifiers for sampling analog signals in response to said second timing signals, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, and having its output terminals connected to said array of N electronic switches, each device being connected to a corresponding one of said switches numbered 1 through N in sequence, andmeans for addressing said memory one row at a time to read out in parallel one row of binary digits from said matrix at a time in response to N timing signals to enable said switches in response to said binary digits.
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Abstract
Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.
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Citations
10 Claims
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1. A hybrid analog-digital neural network comprising
a first random access memory for storing an N× - N matrix of synaptic information in the form of binary 1 and 0 digits,
an array of N analog amplifiers for performing the neuron function of said network, said array of amplifiers being numbered 1 through N corresponding to columns of said matrix, a first array of N electronic switches, each having an input terminal, an output terminal and a control terminal, one switch for each column having its control terminal connected to receive a binary signal of said synaptic information matrix stored in said first memory to enable current to flow through the switch from an input terminal to an output terminal thereof, a first summing amplifier having input and output terminals and a first array of N resistors, one resistor for each of said switches, connecting said switches to the input terminal of said summing amplifier, a first array of N sample-and-hold devices for sampling and holding an output signal at the output terminal of said summing amplifier in response to a control signal, said array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, means for generating first and second timing signals where said first consists of N timing signals for every one of said second timing signals, means for producing and sequentially applying said control signal to said first array of N sample-and-hold devices in response to said first timing signal, said first array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, a second array of N sample-and-hold devices having its input terminals connected to said array of analog amplifiers for sampling analog signals in response to said second timing signals, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, and having its output terminals connected to said array of N electronic switches, each device being connected to a corresponding one of said switches numbered 1 through N in sequence, and means for addressing said memory one row at a time to read out in parallel one row of binary digits from said matrix at a time in response to N timing signals to enable said switches in response to said binary digits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- N matrix of synaptic information in the form of binary 1 and 0 digits,
Specification