Hybrid analog-digital associative neural network

• US 4,807,168 A
• Filed: 06/10/1987
• Issued: 02/21/1989
• Est. Priority Date: 06/10/1987
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Original Assignee: The United States of America As Represented By The Secretary of Agriculture
• Inventors: Thakoor, Anilkumar P., Moopenn, Alexander W., Lambe, John J.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Baker, Stephen M.
• Application Number:
  US07/060,201
• Time in Patent Office: 622 Days
• Field of Search: 364/600, 364/602, 364/513, 364/200 MS File, 364/900 MS File, 364/800, 364/807, 364/135, 307/201, 365/49
• US Class Current: 706/37
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Claims

1. A hybrid analog-digital neural network comprising

a first random access memory for storing an N×

N matrix of synaptic information in the form of binary 1 and 0 digits,

an array of N analog amplifiers for performing the neuron function of said network, said array of amplifiers being numbered 1 through N corresponding to columns of said matrix,

a first array of N electronic switches, each having an input terminal, an output terminal and a control terminal, one switch for each column having its control terminal connected to receive a binary signal of said synaptic information matrix stored in said first memory to enable current to flow through the switch from an input terminal to an output terminal thereof,

a first summing amplifier having input and output terminals and a first array of N resistors, one resistor for each of said switches, connecting said switches to the input terminal of said summing amplifier,

a first array of N sample-and-hold devices for sampling and holding an output signal at the output terminal of said summing amplifier in response to a control signal, said array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence,

means for generating first and second timing signals where said first consists of N timing signals for every one of said second timing signals,

means for producing and sequentially applying said control signal to said first array of N sample-and-hold devices in response to said first timing signal, said first array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence,

a second array of N sample-and-hold devices having its input terminals connected to said array of analog amplifiers for sampling analog signals in response to said second timing signals, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, and having its output terminals connected to said array of N electronic switches, each device being connected to a corresponding one of said switches numbered 1 through N in sequence, and

means for addressing said memory one row at a time to read out in parallel one row of binary digits from said matrix at a time in response to N timing signals to enable said switches in response to said binary digits.

2. A neural network as defined in claim 1 wherein each of said analog amplifiers performing the neuron function of said network includes a second input terminal for receiving a prompt signal and a third input terminal for receiving an inhibit signal which sets a threshold level for the amplifier, every amplifier receiving said inhibit signal, and each amplifier receiving a distinct prompt signal.

3. A neural network as defined in claim 2 including an additional resistor connected to one of said first and second summing amplifiers, and means connected to said additional resistor for producing a prompt signal consisting of N binary 1 and 0 digits in series while said first array of sample-and-hold devices sample the output of said difference amplifier in sequence, thereby storing signals in response to said N prompt digits in said first array of N sample-and-hold devices.

4. A neural network as defined in claim 1 including a second random memory for storing an N×

N matrix of binary 1 and 0 digits, where binary 1 digits represent a negative unit value and may not occupy a position in said second memory corresponding to a position occupied by a binary digit 1 in said first memory, said second memory being addressed in parallel with said first memory,

a second array of N electronic switches, each having an input terminal, an output terminal and a control terminal, one switch for each column having its control terminal connected to receive a binary signal of said synaptic information matrix stored in said second memory to enable current to flow through the switch from an input terminal to an output terminal thereof,

a second summing amplifier and a second array of resistors, one resistor for each of said switches, connecting each of said second array of switches to the input terminal of said summing amplifier, and

a difference amplifier having first and second input terminals connected to output terminals of said first and second summing amplifiers, and an output terminal connected to said second array of sample-and-hold devices.

5. A neural network as defined in claim 1 including a microprocessor, wherein said first memory is addressed one row at a time in response to said first timing signals and said second array of sample-and-hold devices are enabled to sample in parallel by said second timing signal, and said means for generating said first and second timing signals is controlled to run by said microprocessor in response to a control signal.

6. A neural network as defined in claim 5 including means controlled by said microprocessor for monitoring said network to determine after each cycle of said second timing signal when stability has been reached in the operation of the network.

7. A neural network as defined in claim 6 wherein said monitoring means includes means for sampling in sequence and converting the output signals of said analog amplifiers after each matrix cycle for comparison with output signals from previous matrix cycles to determine when stability has been reached.

8. A neural network as defined in claim 7 including a microprocessor, wherein said first memory is addressed one row at a time in response to said first timing signals and said second array of sample-and-hold devices are enabled to sample in parallel by said second timing signal, and said means for generating said first and second timing signals is controlled to run by said microprocessor in response to a control signal.

9. A neural network as defined in claim 8 including means controlled by said microprocessor for monitoring said network to determine after each cycle of said second timing signal when stability has been reached in the operation of the network.

10. A neural network as defined in claim 9 wherein said monitoring means includes means for sampling in sequence and converting the output signals of said analog amplifiers after each second timing signal cycle for comparison with output signals from previous second timing signal cycles to determine when stability has been reached.