Programmable interconnection chip for computer system functional modules

• US 4,807,183 A
• Filed: 06/23/1988
• Issued: 02/21/1989
• Est. Priority Date: 09/27/1985
• Status: Expired due to Fees

• Current Assignee: Carnegie Mellon University
• Original Assignee: Carnegie Mellon University
• Inventors: Hsu, Feng-Hsiung, Kung, Hsiang-Tsung, Nishizawa, Teiji, Sussman, Alan L.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Eakman, Christina M.
• Application Number:
  US07/210,754
• Time in Patent Office: 243 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/736, 364/754
• US Class Current: 710/317
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnection, a FIFO or programmable delay for each of its inputs and a pipeline register file for each of its outputs. By using pre-stored control patterns, the chip can configure its crossbar and delays while performing other operations. Therefore, the usual functions of busses and register files can be realized with this single chip. Various embodiments and applications for the chip are disclosed.

Claims

1. A programmable interconnection chip for use in interconnecting major components of a processor such as arithmetic logic units, floating point multipliers, processor memory and processor register files to provide physical communication and data buffering between such components comprising:

(a) programmable data input buffer and flow control means including a plurality of data input ports;

(b) programmable pipeline register file output means including a plurality of data output ports;

(c) crossbar interconnection means electrically connected between the data input buffer and flow control means and the pipeline register file output means, said crossbar interconnection means configured on each clock cycle to provide a desired interconnection pattern in a manner allowing multiple data transfers to flow in parallel between the data input buffer and flow control means and the pipeline register file output means in accordance with said pattern; and

(d) control pattern memory means electrically connected to the crossbar interconnection means and the pipeline register file output means for storing programmed instructions designed to control the configuration of the interconnection pattern and the operations of the crossbar interconnection means on each clock cycle and to control shifting of data into and output of data from the pipeline register file output means on each clock cycle, said electrical connection of the control pattern memory means to the crossbar interconnection means being independent of said electrical connection between the crossbar interconnection means and the data input buffer and control means.

2. A programmable interconnection chip according to claim 1 wherein each data input buffer and flow control means is programmed to comprise one of a FIFO means and a programmable delay means.

3. A programmable interconnection chip according to claim 1 wherein the crossbar interconnection means is unidirectional and only allows data to flow from the input buffer and flow control means to the pipeline register file output means.

4. A programmable interconnection chip according to claim 1 wherein the control pattern memory means is configured into two memory banks.

6. A programmable interconnection chip according to claim 1 wherein programmed instructions contained in the control pattern memory means determine whether each pipeline register file output means will store a current crossbar interconnection means output.

7. A programmable interconnection chip according to claim 1 in which a minimum delay of one clock cycle results between an input of data into the data input buffer and flow control means and output of data from the pipeline register file output means.

8. A programmable interconnection chip according to claim 1 further comprising delay code register means electrically connected to the data input buffer and flow control means for configuring said data input buffer and flow control means as one of a FIFO means and a programmable delay means.

9. A programmable interconnection chip according to claim 8 wherein the delay code register means sends programmed instructions to each data input buffer and flow control means causing each to be configured as one of a FIFO means and a programmable delay means.

10. A programmable interconnection chip according to claim 1 for use in interconnecting processor components with a maximum data path of n-bits.

11. A programmable interconnection chip according to claim 10 in combination with at least one additional programmable interconnection chip for use in interconnecting components of a processor with data paths wider than n-bits, said programmable interconnection chip and said at least one additional programmable interconnection chip being electrically interconnected.

12. A programmable interconnection chip according to claim 11 in combination with at least one additional programmable interconnection chip for use in interconnecting components of a processor wherein each input port of said programmable interconnection chip is interconnected to a corresponding input port of said at least one additional programmable interconnection chip.

13. A programmable interconnection chip according to claim 11 in combination with at least one additional programmable interconnection chip for use in interconnecting components of a processor wherein each output port of said programmable interconnection chip is interconnected to a corresponding output port of said at least one additional programmable interconnection chip by tri-stating whereby at most one of said interconnected output ports is enabled on each clock cycle.

14. A programmable interconnection chip according to claim 11 in combination with a second, third and fourth additional programmable interconnection chip wherein each input port of said programmable interconnection chip and said third programmable interconnection chip is interconnected to a corresponding input port of said second and said fourth programmable interconnection chips, respectively, and each output port of said programmable interconnection chip and said second programmable interconnection chip is interconnected to a corresponding output port of said third and forth chips, respectively, by tri-stating whereby at most one of said interconnected output ports is enabled on each clock cycle.

15. A programmable interconnection chip according to claim 10 having a generally rectangular shape and having input ports provided along one edge thereof and output ports provided along an adjacent edge thereof.

16. A programmable interconnection chip according to claim 15, in combination with a second, third and fourth programmable interconnection chip, each of said second, third and fourth programmable interconnection chips being provided in a common plane with said programmable interconnection chip, said programmable interconnection chip and said second programmable interconnection chip being longitudinally juxtaposed, said third and fourth programmable interconnection chips being longitudinally juxtaposed, said programmable interconnection chip and said third programmable interconnection chip being transversely juxtaposed and said second and said fourth programmable interconnection chips being transversely juxtaposed whereby a compact and regular layout of interconnection lines between chips is provided.

5. A programmable interconnection chip according to claim wherein one of said two memory banks may be programmed with new control patterns while the other of said two banks controls the configuration and operation of the crossbar interconnection means and pipeline register file output means.