Redundancy for a block-architecture memory

• US 4,807,191 A
• Filed: 01/04/1988
• Issued: 02/21/1989
• Est. Priority Date: 01/04/1988
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Flannagan, Stephen T.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/140,706
• Time in Patent Office: 414 Days
• Field of Search: 365/189, 365/200, 365/230
• US Class Current: 714/711
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

A block architecture memory has two stacks of memory blocks. Between the two stacks are blocks of sense amplifiers. Each block of sense amplifiers is coupled to a memory block in each of the stacks of memory blocks via local data lines. Located at the bottom of each stack of memory blocks is a redundant block of columns of memory cells. There is a redundant sense amplifier located between and coupled to the redundant blocks of columns via local data lines. The redundant sense amplifier is also coupled to a redundant global data line. An input/output multiplexer is coupled to all of the global data lines. The multiplexer provides and receives external data. If one of the redundant columns is to replace a defective column for a particular address, then the redundant global data line carries data which corresponds to the external data.

Claims

1. A memory having a read mode and a write mode, comprising:

a plurality of sub-arrays comprised of intersecting rows and columns of memory cells;

a plurality of sets of local data line pairs, each set of local data lines coupled to a corresponding sub-array for carrying data to and from selected columns of the particular sub-array to which the set of local data lines corresponds;

block-select means, coupled to the plurality of sub-arrays, for enabling a particular sub-array as determined by a first set of address signals;

a set of global data lines for carrying data which corresponds to the data carried by the set of local data lines which corresponds to the enabled sub-array;

first sense amplifier means, coupled to the plurality of sets of local data line pairs and the set of global data line pairs, for coupling data between the set of global data lines and the set of local data lines which corresponds to the selected sub-array;

a block of redundant columns;

a redundant local data line pair for carrying data to and from the block of redundant columns;

a redundant global data line pair for carrying data;

second sense amplifier means, coupled to the block of redundant columns via the redundant local data line pair, for coupling data between the redundant global data line pair and the redundant local data line pair;

detection means for detecting when a column in the block of redundant columns is to replace a column in one of the sub-arrays of the plurality of sub-arrays;

multiplexer means, coupled to the detection means, the redundant global data line pair, and the set of global data line pairs, for outputting external data which corresponds to the data present on the redundant global data line when the memory is in the read mode and the detection means detects that a column in the block of redundant columns is to replace a column in one of the sub-arrays and for providing, onto the redundant global data line pair, external data which has been received when the memory is in the write mode and the detection means detects that a column in the block of redundant columns is to replace a column in one of the sub-arrays.

2. The memory of claim 1 wherein each sub-array has coupled thereto a column decoder circuit which couples data between the set of local data line pairs and the selected columns of the corresponding sub-array.

3. The memory of claim 2 wherein the first amplifier means comprises a plurality of sets of amplifier circuits, wherein each set of amplifier circuits is coupled to two sub-arrays.

4. The memory of claim 3 wherein the block-select means is further characterized as enabling the set of amplifier circuits which is coupled to the enabled sub-array.

5. A memory having a read mode and a write mode, comprising:

a plurality of sub-arrays, each sub-array comprised of memory cells located at intersections of word lines and bit line pairs, said sub-arrays arranged in two columns;

a plurality of sets of local data line pairs, each set of local data lines coupled to a corresponding sub-array for carrying data to and from selected bit line pairs of the particular sub-array to which the set of local data lines corresponds;

block-select means, coupled to the plurality of sub-arrays, for enabling a particular sub-array as determined by a first set of address signals;

a plurality of column decoder circuits, each column decoder circuit coupled to a corresponding sub-array for coupling data between the selected bit line pairs and the corresponding set of local data lines;

a set of global data lines for carrying data which corresponds to the data carried by the set of local data lines which corresponds to the enabled sub-array, said set of global data lines located between the columns of sub-arrays;

a plurality of sets of sense amplifier means located between the two columns of sub-arrays, each set of sense amplifier means coupled to one sub-array in each of the two columns of sub-arrays for amplifying and coupling data between the set of global data lines and the set of local data lines which corresponds to the selected sub-array;

first and second blocks of redundant memory cells coupled to redundant bit line pairs located at the bottom of the first and second columns of sub-arrays, respectively;

first and second redundant local data line pairs for carrying data to and from the first and second blocks of redundant memory cells, respectively;

a redundant global data line pair for carrying data;

redundant sense amplifier means, located between and coupled to the first and second blocks of redundant memory cells via the first and second redundant local data line pairs, respectively, for amplifying and coupling data between the redundant global data line pair and the first and second redundant local data line pairs;

detection means for detecting when a bit line pair in one of the first and second blocks of redundant columns is to replace a bit line pair in one of the sub-arrays of the plurality of sub-arrays; and

multiplexer means, coupled to the detection means, the redundant global data line pair, and the set of global data line pairs, for outputting external data which corresponds to the data present on the redundant global data line when the memory is in the read mode and the detection means detects that a column in the block of redundant columns is to replace a column in one of the sub-arrays and for providing, onto the redundant global data line pair, external data which has been received when the memory is in the write mode and the detection means detects that a column in the block of redundant columns is to replace a column in one of the sub-arrays.

6. The memory of claim 5 wherein the block-select means is further characterized as enabling the set of sense amplifier mean which is coupled to the enabled sub-array.

7. A block-architecture memory having a plurality of memory blocks in which each memory block is comprised of a plurality of intersecting rows and columns of memory cells, wherein a block is selectively enabled for providing and receiving data via the columns of memory cells thereof, comprising:

a first stack of said memory blocks arranged from top to bottom;

a second stack of said memory blocks arranged from top to bottom;

a plurality of blocks of sense amplifiers located between the first and second stacks of memory blocks, each block of sense amplifiers coupled to a particular memory block in each of the first and second stacks of said memory blocks;

a first block of redundant columns of memory cells, located at the bottom of the first stack of memory blocks, for replacing defective columns of memory cells in any of said memory blocks of the first stack of said memory blocks;

a second block of redundant columns of memory cells, located at the bottom of the second stack of said memory blocks, for replacing defective columns of memory cells in any of said memory blocks of the second stack of said memory blocks; and

a redundant sense amplifier coupled to and located between the first and second blocks of redundant columns of memory cells.

8. The memory of claim 7 wherein the number of memory blocks in each of the first and second stacks is greater than two.