Programmable P/C compatible communications card

• US 4,807,282 A
• Filed: 12/30/1985
• Issued: 02/21/1989
• Est. Priority Date: 12/30/1985
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kohake, Ronald W., Kazan, Howard
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/814,436
• Time in Patent Office: 1,149 Days
• Field of Search: 364/200 MS File, 364/200, 364/900, 379/94, 379/28, 379/96, 379/284, 379/269, 379/274, 379/290
• US Class Current: 379/284
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A multi-protocol communications adapter (MPCA) is used to interconnect a Local Area Network (such as a store computing system) to a communications highway. The MPCA includes a plurality of protocol controllers, each one of the controllers being operable for converting a data stream into a predetermined format. A programmable configuration register is provided for selecting one of the protocol controllers. A controlled interface is provided for gating the selected controller onto the communications highway. The MPCA is packaged as a card or module. It is coupled to a primary computer that controls the Local Area Network. The primary computer may effectuate a protocol change by changing the contents of the configuration register. Thus, the MPCA can be used with a pre-existing primary computer without significantly changing the architecture and/or programming of said computer.

Claims

1. A multi-protocol communications adapter circuit for use in a telephone communication system or network for interfacing a processor with a modem for providing communication between said processor and a remote host computer via said communication system or network, comprising;

a common communications channel which includes a programmable configuration register for storing control information generated by the processor, said control information representative of one of a plurality of protocols to be used to format data to be transmitted to the remote host computer by means of said communication system or network;

a configuration control logic circuit means coupled to said register;

said configuration control logic circuit means operable to monitor the contents of the register and for generating a plurality of control signals therefrom;

address decoding means coupled to an address bus of said processor;

said address decoding means being operable for generating and outputting enable signals if activated by the control signals and if a predetermined address range is being decoded on the address bus; and

a plurality of protocol conversion controllers coupled to the address decoding means, each one being responsive to the enabling signals and operable for receiving or transmitting a data stream and for converting said data stream into a predetermined protocol format for transmission through said communications system or network.

2. The multi-protocol communications adapter circuit of claim 1 further including a logic circuit control means coupled to the outputs of the protocol conversion controllers;

said logic circuit control means being operable when activated for permitting data from one of said protocol conversion controllers to pass through and for generating at least one interrupt control signal and a direct memory access (DMA) control signal.

3. The multi-protocol communication adapter of claim 1 wherein the configuration control logic circuit means further includes a configuration address register decoder means having its inputs coupled to an address bus of the processor and its output coupled to the configuration register;

a decoder means coupled to the configuration register and operable for generating a plurality of outputs; and

a plurality of "OR" circuits each one being coupled to selected ones of the plurality of outputs.

4. The multi-protocol communications adapter circuit of claim 1 wherein the address decoding means includes a plurality of individual address decoders, each one being operable for decoding a pre-assigned address range;

and

a plurality of logical "AND" circuits each one being connected to one of the individual address decoders and operable when activated for passing signals from one of the decoders.

5. The multi-protocol communications adapter circuit of claim 1 wherein the plurality of protocol conversion controllers include an SDLC controller, a bisynchronous controller and an asynchronous controller.